Pseudo-instructionsAssembly vs. machine languageR-type formatMIPS registersJ-type formatI-type formatLoading larger constantsBranchesLarger branch constantsPseudo-branchesImplementing pseudo-branchesTranslating an if-then statementTranslating an if-then-else statementsControl-flow ExamplePointers & Pointer ArithmeticWhat is a Pointer?What is really going on here…Summary1Pseudo-instructionsMIPS assemblers support pseudo-instructions that give the illusion of a more expressive instruction set, but are actually translated into one or more simpler, “real” instructions.In addition to the li (load immediate) we saw on last lecture, you can use the move and la pseudo-instructions:move $a1, $t0 # Copy $t0 into $a1la $a0, data # Load address of memory labeled # ‘data’ into $a0Simpler, clearer than equivalent MIPS instructions.We’ll see lots more pseudo-instructions this semester.—A complete list of instructions is given in Appendix A of the text.Unless otherwise stated, you can always use pseudo-instructions in your assignments and on exams.For now, we’ll focus on real instructions…2Assembly vs. machine languageSo far we’ve been using assembly language.—We assign names to operations (e.g., add) and operands (e.g., $t0).—Branches and jumps use labels instead of actual addresses.—Assemblers support many pseudo-instructions.Programs must eventually be translated into machine language, a binary format that can be stored in memory and decoded by the CPU.MIPS machine language is designed to be easy to decode.—Each MIPS instruction is the same length, 32 bits.—There are only three different instruction formats, which are very similar to each other.—The format of an instruction is determined by its first 6 bits, known as the operation code, or opcode.Studying MIPS machine language will also reveal some restrictions in the instruction set architecture, and how they can be overcome.3R-type formatRegister-to-register arithmetic instructions use the R-type format.This format includes six different fields.—opcode is an operation code that selects a specific operation.—rs and rt are the first and second source registers.—rd is the destination register.—shamt is only used for shift instructions.—func is used together with opcode to select an arithmetic instruction. The inside back cover of the textbook lists opcodes and function codes for all of the MIPS instructions.opcode rs rt rd shamt func6 bits 5 bits 5 bits 5 bits 5 bits 6 bits4MIPS registersWe have to encode register names as 5-bit numbers from 00000 to 11111.—For example, $t8 is register $24, which is represented as 11000.—The complete mapping is given on page A-23 in the book.The number of registers available affects the instruction length.—Each R-type instruction references 3 registers, which requires a total of 15 bits in the instruction word.—We can’t add more registers without either making instructions longer than 32 bits, or shortening other fields like opcode and possibly reducing the number of available operations.squeezed5 bitswidewidewidesqueezedfuncshamtrdrtrsopcode5J-type formatThe j and jal instructions use the J-type instruction format.Last 26 bits: word address of the target instruction—Remember that each MIPS instruction is one word long, and word addresses must be divisible by four.—So instead of saying “jump to address 4036,” it’s enough to just say “jump to instruction 1009”.—A 26-bit address field lets you jump to any address from 0 to 228.•your MP solutions had better be smaller than 256MBFor even longer jumps, the jump register (jr) instruction can be used.jr $ra # Jump to 32-bit address in register $raopcode address6 bits 26 bits6I-type formatLoad, store, branch and immediate instructions all use the I-type format.For uniformity, opcode, rs and rt are located as in the R-format.The meaning of the register fields depends on the exact instruction.—rs is always a source register—an address for loads and stores, or an operand for branch and immediate arithmetic instructions.—rt is a source register for branches and stores, but a destination register for the other I-type instructions.The immediate is a 16-bit signed two’s-complement value.—It can range from -32,768 to +32,767.—But that’s not always enough! E.g. how do you load a 32-bit constant into a register?opcode rs rt immediate6 bits 5 bits 5 bits 16 bits7Larger constants can be loaded into a register 16 bits at a time.—The load upper immediate instruction lui loads the highest 16 bits of a register with a constant, and clears the lowest 16 bits (sets to 0s).—An immediate logical OR, ori, then sets the lower 16 bits.To load the 32-bit value 0000 0000 0011 1101 0000 1001 0000 0000:lui $s0, 0x003D # $s0 = 003D 0000 (in hex)ori $s0, $s0, 0x0900 # $s0 = 003D 0900This illustrates the principle of making the common case fast.—Most of the time, 16-bit constants are enough.—It’s still possible to load 32-bit constants, but at the cost of two instructions and one temporary register.Pseudo-instructions may contain large constants. Assemblers including SPIM will translate such instructions correctly.Loading larger constants8For branch instructions, the constant field is not an address, but an offset from the current program counter (PC) to the target address.L0: beq $at, $0, L4L1: add $v1, $v0, $0L2: add $v1, $v1, $v1L3: j SomewhereL4: add $v1, $v0, $v0Since the branch target L4 is four instructions past the beq, the address field contains 4. The whole beq instruction would be stored as:Branches00010000001 00000 0000 0000 0000 0100op rs rt address9Empirical studies of real programs show that most branches go to targets less than 32,767 instructions away—branches are mostly used in loops and conditionals, and programmers are taught to make code bodies short.If you do need to branch further, you can use a jump with a branch. For example, if “Far” is very far away, then the effect of:beq $s0, $s1, Far...can be simulated with the following actual code.bne $s0, $s1, Nextj FarNext: ...Again, the MIPS designers have taken care of the common case first.Larger branch constants10The MIPS processor only supports two branch instructions, beq and bne, but to simplify your life the assembler provides the following other branches: blt $t0, $t1, L1 // Branch if $t0 <
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