EE 245: Introduction to MEMSLecture 11: Bulk MicromachiningCTN 10/1/09Copyright © 2009 Regents of the University of CaliforniaEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 47“Foundry” MEMS:The MUMPS ProcessEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 48MUMPS: MMultiUUser MEMS PProcesSS• Originally created by the Microelectronics Center of North Carolina (MCNC) → now owned by MEMSCAP in France• Three-level polysilicon surface micromachining process for prototyping and “foundry” services• Designed to service as many users as possible; basically an attempt to provide a universal MEMS process• 8 photomasks• $4,900 for 1 cm2diesMicromotor fabricated via MUMPSEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 49MUMPS: MMultiUUser MEMS PProcesSSMicromotor ExampleEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 50Masks in polyMUMPS• Field type:ª Light (or clear) field (cf): in layout, boxes represent features that will stay through fabricationª Dark field (df): in layout, boxes represent holes to be cut outMinimum set of masks that must be used in MUMPSMinimum set of masks that must be used in MUMPSExtra masks for more flexibility & ease of releaseExtra masks for more flexibility & ease of releaseEE 245: Introduction to MEMSLecture 11: Bulk MicromachiningCTN 10/1/09Copyright © 2009 Regents of the University of CaliforniaEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 51MUMPS Process Flow• Deposit PSG on the starting n-type (100) wafers • Anneal to heavily dope the wafers• Remove the PSG• LPCVD 600 nm of low stress nitride• LPCVD 500 nm of polysilicon• Lithography using the POLY0(cf) mask and RIE etching to pattern the poly0 ground plane layer• LPCVD 2 μm of PSG as the 1stsacrificial layer• Lithography using the DIMPLE(df) mask (align to poly0)• RIE 750 nm deep to form dimple vias• Lithography using the ANCHOR1 (df) mask (align to poly0)• RIE anchor vias down to the nitride surfaceEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 52MUMPS Process Flow (cont.)• LPCVD 2 μm undoped polysilicon• LPCVD 200 nm of PSG• Anneal for 1 hr. @ 1050oCª This both dopes the polysilicon and reduces its residual stress• Lithography using the POLY1(cf) mask to define structures (align to anchor1)• RIE the PSG to create a hard mask first, then …• RIE the polysilicon• LPCVD 750 nm of PSG• Lithography using the P1_P2_VIA (df) mask to define contacts to the poly1 layer (align to poly1)EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 53MUMPS Process Flow (cont.)• Recoat with photoresist and do lithography using the ANCHOR2(df) mask to define openings where poly2 contacts nitride or poly0 (align to poly0)• RIE the PSG at ANCHOR2 openings• LPCVD 1.5 μm undoped polysilicon• LPCVD 200 nm PSG as a hard mask and doping source• Anneal for 1 hr @ 1050oC to dope the polysilicon and reduce residual stress• Lithography using the POLY2(cf) mask (align to anchor2)• RIE PSG hard mask• RIE poly2 film• Remove PR and hard maskEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 54MUMPS Process Flow (cont.)• Lithography using the METAL (df) mask (align to poly2)• Evaporate titanium (Ti) (as an adhesion layer for gold)• Evaporate gold (Au)• Liftoff to remove PR and define metal interconnects• Coat wafers with protective PR• Dice wafers• Ship to customer• Customer releases structures by dipping and agitating dies in a 48.8 wt. % HF solution or via vapor phase HF• Anti-stiction dry, if neededPoly1 RotorPoly1 StatorFinal Structure: MicromotorEE 245: Introduction to MEMSLecture 11: Bulk MicromachiningCTN 10/1/09Copyright © 2009 Regents of the University of CaliforniaEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 55MUMPS: MMultiUUser MEMS PProcesSS• Originally created by the Microelectronics Center of North Carolina (MCNC) → now owned by MEMSCAP in France• Three-level polysilicon surface micromachining process for prototyping and “foundry” services• Designed to service as many users as possible; basically an attempt to provide a universal MEMS process• 8 photomasks• $4,900 for 1 cm2diesMicromotor fabricated via MUMPSEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 56polyMUMPS Minimum Feature Constraints• Minimum feature sizeª Determined by MUMPS’ photolithographic resolution and alignment precisionª Violations result in missing (unanchored), under/oversized, or fused featuresª Use minimum feature only when absolutely necessaryNominal [μm]Min Feature [μm]Min Spacing [μm]POLY0, POLY1, POLY2 3 2 2POLY1_POLY2_VIA 3 2 2ANCHOR1, ANCHOR2 3 3 2DIMPLE 3 2 3METAL 3 3 3HOLE1, HOLE2 4 3 3HOLEM 5 4 4EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 57MUMPS Design RulesCross SectionsMask LevelsPOLY0ANCHOR1Oxide1Poly0EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 58MUMPS Design Rules (cont.)POLY0ANCHOR1Cross SectionsMask LevelsPoly1Oxide1POLY1Poly0GNHOKREE 245: Introduction to MEMSLecture 11: Bulk MicromachiningCTN 10/1/09Copyright © 2009 Regents of the University of CaliforniaEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 59MUMPS Design Rules (cont.)EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 60MUMPS Design Rules (cont.)EE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 61The Sandia SUMMIT ProcessEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 62Sandia’s SUMMiT V• SUMMiT V: “Sandia Ultra-planar Multi-level MEMS Technology 5” fabrication processª Five-layer polysilicon surface micromachining processª One electrical interconnect layer & 4 mechanical layersª Uses chemical mechanical polishing (CMP) to maintain planarity as more structural layers are realizedª 14 masksEE 245: Introduction to MEMSLecture 11: Bulk MicromachiningCTN 10/1/09Copyright © 2009 Regents of the University of CaliforniaEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 63SUMMiT V Layer Stack• Uses chemical mechanical polishing (CMP) to maintain planarity as more structural layers are realizedEE C245: Introduction to MEMS Design LecM 5 C. Nguyen 8/20/09 64Chemical Mechanical Polishing (CMP)• Used to planarize the top surface of a semiconductor wafer or other substrate• Uses an abrasive and corrosive chemical slurry
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