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1© 2005 Microchip Technology Incorporated. All Rights Reserved. Slide 1PIC18 ReviewArchitecture, Instruction Set, and Assembly Language ProgrammingArchitecture The high performance of the PICmicro®microcontroller can be attributed to the following architectural features: Harvard Architecture Instruction Pipelining Large Register File (RISC) Single Cycle Instructions Single Word Instructions Long Word Instructions (Harvard) Reduced Instruction Set  Orthogonal Instruction SetHarvard Architecture Von Neumann Architecture: Fetches instructions and data from a single memory space Limits operating bandwidth Harvard Architecture: Uses two separate memory spaces for program instructions and data Improved operating bandwidth Allows for different bus widths2Instruction Pipelining Instruction fetch is overlaped with execution of previously fetched instructionrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0FlushT1 T2 T3 T4 T5Instruction CyclesT6Fetch ExecuteFetch ExecuteFetchFetch ExecuteFetch ExecuteFetch FlushFetchT7Time to execute normal instructionTime to execute call instruction includes pipeline flushInstruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetchT0Instruction Cyclesmovlw 0x05 -Pre-Fetched InstructionExecuting InstructionInstruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0 T1Instruction CyclesFetchmovwf REG1 movlw 0x05Pre-Fetched InstructionExecuting Instruction3Instruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0 T1 T2Instruction CyclesFetch ExecuteFetchrcall SUB1 movwf REG1Pre-Fetched InstructionExecuting InstructionTime to execute normal instructionInstruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0 T1 T2 T3Instruction CyclesFetch ExecuteFetch ExecuteFetchaddwf REG2 rcall SUB1Pre-Fetched InstructionExecuting InstructionInstruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0FlushT1 T2 T3 T4Instruction CyclesFetch ExecuteFetch ExecuteFetchFetchmovf PORTB,w rcall SUB1Pre-Fetched InstructionExecuting InstructionTime to execute call instruction includes pipeline flush4Instruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0FlushT1 T2 T3 T4 T5Instruction CyclesFetch ExecuteFetch ExecuteFetchFetch ExecuteFetchreturn movf PORTB,wPre-Fetched InstructionExecuting InstructionInstruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0FlushT1 T2 T3 T4 T5Instruction CyclesT6Fetch ExecuteFetch ExecuteFetchFetch ExecuteFetch ExecuteFetchmovf PORTC,w returnPre-Fetched InstructionExecuting InstructionInstruction Pipeliningrcall SUB1addwf REG2movf PORTB,wreturnmovf PORTC,wreturnSUB1SUB2movlw 0x05MAINmovwf REG1123451525354Example ProgramFetch ExecuteT0FlushT1 T2 T3 T4 T5Instruction CyclesT6Fetch ExecuteFetch ExecuteFetchFetch ExecuteFetch ExecuteFetch FlushFetchT7addwf REG2 returnPre-Fetched InstructionExecuting Instruction500000000Long Word Instruction8-bit Program Memory16-bit Program Memory1100000000111100kkkkkkkkkkkkkkkk11111100kkkkkkkkkkkkkkkk8-bit Instruction on typical 8-bit MCUExample: Freescale ‘Load Accumulator A’:• 2 Program Memory Locations• 2 Instruction Cycles to Execute16-bit Instruction on PIC18 8-bit MCUExample: ‘Move Literal to Working Register’• 1 Program Memory Location• 1 Instruction Cycle to Execute Limits Bandwidth Increases Memory Size Requirements Separate busses allow different widths 2k x 16 is roughly equivalent to 4k x 8ldaa #kmovlw kRegister File ConceptData BusData BusdDecoded Instruction from Program Memory:Arithmetic/Logic Function to be PerformedResult DestinationAddress of Second Source Operand Register File Concept: All of data memory is part of the register file, so any location in data memory may be operated on directly All peripherals are mapped into data memory as a series of registers Orthogonal Instruction Set: ALL instructions can operate on ANY data memory location The Long Word Instruction format allows a directly addressable register filewfwfALUWREGWREGData Memory(Register File)07h08h09h0Ah0Bh0Ch0Dh0Eh0Fh10hOpcodeOpcodeddaaAddressAddressByte Oriented OperationsByte Oriented OperationsPIC18 Instruction Set Overviewaddwf f,d,aaddwf f,d,aaddwfc f,d,aaddwfc f,d,aandwf f,d,aandwf f,d,aclrf f,aclrf f,acomf f,d,acomf f,d,acpfseq f,acpfseq f,acpfsgt f,acpfsgt f,acpfslt f,acpfslt f,adecf f,d,adecf f,d,adecfsz f,d,adecfsz f,d,adcfsnz f,d,adcfsnz f,d,aincf f,d,aincf f,d,aincfsz f,d,aincfsz f,d,ainfsnz f,d,ainfsnz f,d,aiorwf f,d,aiorwf f,d,amovf f,d,amovf f,d,amovff fs,fdmovff fs,fdmovwf f,amovwf f,amulwf f,amulwf f,anegf f,anegf f,arlcf f,d,arlcf f,d,arlncf f,d,arlncf f,d,arrcf f,d,arrcf f,d,arrncf f,d,arrncf f,d,asetf f,asetf f,asubfwb f,d,asubfwb f,d,asubwf f,d,asubwf f,d,asubwfb f,d,asubwfb f,d,aswapf f,d,aswapf f,d,atstfsz f,atstfsz f,axorwf f,d,axorwf f,d,aAdd WREG and fAdd WREG and fAdd WREG and Carry bit to fAdd WREG and Carry bit to fAND WREG with fAND WREG with fClear fClear fComplement fComplement fCompare f with WREG, skip =Compare f with WREG, skip =Compare f with WREG, skip >Compare f with WREG, skip >Compare f with WREG, skip <Compare f with WREG, skip <Decrement fDecrement fDecrement f, Skip if 0Decrement f, Skip if 0Decrement f, Skip if Not 0Decrement f, Skip if Not 0Increment fIncrement fIncrement f, Skip if 0Increment f, Skip if 0Increment f, Skip if Not 0Increment f, Skip if Not 0Inclusive OR WREG with fInclusive OR WREG with fMove fMove fMove fs(src) to fd(dst)Move fs(src) to fd(dst)Move WREG to fMove WREG to fMultiply WREG with fMultiply WREG with fNegate fNegate fRotate Left f through CarryRotate Left f through CarryRotate Left f (No Carry)Rotate Left f (No Carry)Rotate Right f through CarryRotate Right f through CarryRotate Right f (No Carry)Rotate Right f (No Carry)Set fSet fSubtract f from WREG


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SSU ES 310 - PIC18 Review

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