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Performance Modeling and Noise Reduction in VLSI Packaging

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October 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 1Performance Modeling and Noise Reductionin VLSI PackagingPh.D. DefenseBrock J. LaMeresUniversity of Colorado October 7, 2005October 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 2Problem Statement• VLSI Packaging Limits System Performance1) Supply Bounce2) Signal Coupling3) Bandwidth Limitation4) Impedance Discontinuities5) Cost & ScalingOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 3Agenda1) Problem Motivation2) Research Overview3) Advantages Over Prior Techniques4) Broader Impact of this WorkOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 41) Problem MotivationOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 5Why is packaging limiting performance?• IC Design/Fabrication is Outpacing Package Technology- We’re seeing exponential increase in IC transistor performance- >1.3 Billion transistors on 1 die [Fall IDF-05]October 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 6Why is packaging limiting performance?• Packages Have Been Designed for Mechanical Performance- Electrical performance was not primary consideration- IC’s limited electrical performance- Package performance was not the bottleneckOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 7Why is packaging limiting performance?• VLSI Performance Exceeds Package Performance- Packages optimized for mechanical reliability, but still used due to cost- IC performance far exceeds package performanceOn-Chip-fIC > 4GHz- large signal counts- exponential scalingPackage-fpkg < 2GHz- limited signal counts- linear scalingOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 8Why is packaging limiting performance?• Package Interconnect Contains Parasitic Inductance and Capacitance - Long interconnect paths- Large return loops--Wire Bond Inductance (~2.8nH)LIΦ=QACVtε==BGA Capacitance (~300fF)October 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 9Why is packaging limiting performance?• Package Parasitics Limit Performance- Excess L and C causes package noise- Noise limits how fast the package can transmit date1) Supply Bounce2) Signal Coupling3) Bandwidth Limiting4) Impedance DiscontinuitiesOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 10Why is packaging limiting performance?• Aggressive Package Design Helps, but is expensive…- 95% of VLSI design-starts are wire bonded- Goal: Extend the life of current packagesQFP – Wire Bond : 4.5nH → $0.22 / pinBGA – Wire Bond : 3.7nH → $0.34 / pin *** BGA – Flip-Chip : 1.2nH → $0.63 / pinOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 112) Research OverviewOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 12Research Overview• Performance Modeling & Bus Sizing- algebraic model to predict performance and cost-effectiveness• Bus Expansion CODEC- encoding data to avoid patterns on bus which cause excessive noise• Bus Stuttering CODEC- encoding data to avoid patterns on bus which cause excessive noise• Impedance Compensation- adding C or L near package to match impedance to systemOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 13- “FPGA I/O – When to go serial”, IEE Electronic Systems and Software, 2004- “Performance Model for Inter-Chip Busses Considering Bandwidth and Cost”DesignCon, 2005- “Performance Model for Inter-chip Com Considering Inductive Cross-talk and Cost”,ISCAS, 2005- “Performance Model for Inter-Chip Busses Considering Bandwidth and Cost”,DesignConEast, 2005- “Package Performance Model for Off-chip Busses Considering Bandwidth and Cost”,IEE Journal on Computers and Digital Techniques(accepted for publication)Publications: Performance Modeling and Bus Sizing•Best Paper AwardOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 14- “Encoding-based Minimization of Inductive Cross-talk for Off-chip Data Transmission”, DATE, 2005- “Controlling Inductive Cross-talk and Power in Off-chip Buses using CODECS”, ASP-DAC 2006 (accepted for publication)- “Bus Stuttering: An Encoding Technique to Reduce Inductive Noise in Off-Chip Data”, DATE 2006 (submitted)Publications: Bus CODECs to Avoid Package NoiseOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 15- “Time Domain Analysis of a Printed Circuit Board Via”, Microwave Journal, 2000- “The Effect of Ground Vias on Changing Signal Layers in Multi-Layered PCBs”, Microwave and Optical Technology Letters, 2001 - “Broadband Impedance Matching for Inductive Interconnect in VLSI Packages”, ICCD, 2005- “Impedance Matching Techniques for VLSI Packaging”, DesignCon, 2006 (accepted for publication)Publications: Impedance Compensation•Best Paper AwardOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 16Performance Modeling• Analytical Model To Predict Bus Performance– VLSI/CAD integration– Quick hand calculations• We Can Use Package Noise As the Failure Parameter– Any noise source can be used as limit– Max (di/dt) or (dv/dt) is extracted and converted to bus throughputNOISEv(t)tp•VDD VDDNewOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 17Performance Modeling• Bus Notation- Analysis performed on repetitive segment, reducing computation time- A scalable framework is used to represent the bus configurationG S PS S S G S S P S S G S SP S SWbussegment (j-1) segment (j) segment (j+1)M12M12M13M13M1(pL)M1(pL)C12C12C13C13C1(pC)C1(pC)L11, C0Mutual CapacitanceMutual InductanceSelf Inductance, Capacitance(Ng, Np)NewOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 18Performance Modeling• Use Ground Bounce as Failure Mechanism()21|(| | 1) 0111|(| | 1)0.8CLLCppkbusgnd bnc k DDkp kpkk kgCZLWdi di diVM pVNdt dt dt+−+=− =−⎛⎞⎛⎞⋅⋅⎛⎞ ⎛⎞ ⎛⎞=+⋅+ ⋅=⋅⎜⎟⎜⎟⎜⎟ ⎜⎟ ⎜⎟⎜⎟⎜⎟⎝⎠ ⎝⎠ ⎝⎠⎝⎠⎝⎠∑∑Self ContributionG S PS S S G S S P S S G S S PP S SMutual Inductive ContributionMutual Capacitive ContributionNoiseLimitNewOctober 7, 2005 “Performance Modeling and Noise Reduction in VLSI Packaging” 19∴


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