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GT ECE 6414 - HIGH SPEED ANALOG-DIGITAL CONVERTERS

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CMOS Analog IC Design Page 10.8-1 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 10.8 - HIGH SPEED ANALOG-DIGITAL CONVERTERS Conversion time is T where T is a clock period. Types: • Parallel or Flash ADCs • Interpolating ADCs • Folding ADCs • Speed-Area Tradeoffs - Multiple-Bit, Pipeline ADCs - Digital Error Correction • Time-Interleaved ADCsCMOS Analog IC Design Page 10.8-2 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 PARALLEL OR FLASH ANALOG-DIGITAL CONVERTER A 3-bit, parallel ADC: Comments: • Fast, in the first phase of the clock the analog input is sampled and applied to the comparators. In the second phase, the digital encoding network determines the correct output digital word. • Number of comparator required is 2N-1 • Can put a sample-hold at the input or can used clocked comparatorsCMOS Analog IC Design Page 10.8-3 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 • Typical sampling frequencies can be as high as 400MHz for 6-bits in sub-micron CMOS technology.CMOS Analog IC Design Page 10.8-4 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 EXAMPLE 10.8-1 Influence of the Comparator Offset on the ADC Performance Two comparators are shown of an N-bit flash ADC. Comparators 1 and 2 have an offset voltage indicated as VOS1 and VOS2, respectively. A portion of the ideal transfer function of the converter is also shown. (a.) When do the comparator offsets cause a missing code? Express this condition in terms of VOS1, VOS2, N, and VREF. (b.) Assume all offsets are identical and express the magnitude of INL in terms of VOS1(=VOS2), N, and VREF. (c.) Express the DNL in terms of VOS1, VOS2, N, and VREF. Solution (a.) We note that comparator 1 changes from a 0 to 1 when Vin(1) > VR1-VOS1 and comparator 2 changes from a 0 to 1 when Vin(2) > VR2-VOS2. A missing code will occur if Vin(2) < Vin(1). Therefore, VR2 - VOS2 > VR1 - VOS1 → VR2 - VR1 > VOS2 - VOS` But, VR2 - VR1 = VREF2N → |VOS2 - VOS1| < VREF2N .CMOS Analog IC Design Page 10.8-5 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 EXAMPLE 10.8-1 - CONTINUED (b.) If all offsets are alike and equal to VOS, we can write that the INL is given as the worst case deviation about each VRi INL = |VOS|VLSB = |VOS|VREF/2N = 2N |VOS|VREF . (c.) The DNL can be expressed as the worst case difference between the offset deviations as DNL = (VR2 - VOS2) - (VR1 - VOS1) - VLSBVLSB = VLSB + VOS2 - VOS1 - VLSBVLSB = |VOS2 - VOS1|VLSB = 2N |VOS2 - VOS1|VREFCMOS Analog IC Design Page 10.8-6 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 PHYSICAL CONSEQUENCES OF HIGH SPEED CONVERTERS Assume that clocked comparators are used in a 400MHz sampling frequency ADC of 6-bits. If the input frequency is 200MHz with a peak-to-peak value of VREF,, the clock accuracy must be ∆t ≤ ∆VωVp = VREF/2N+1 2πf(0.5VREF) = 127·π·f = 12.5ps Since electrical signals travel at approximately 1ps/µm for metal on an IC, the length of the metal path from the clock to each comparator must be equal to within 12.5µm. Therefore, must use careful layout to avoid ADC inaccuracies at high frequencies. Equal-delay,clock distribution system for a 4-bit parallel ADC:CMOS Analog IC Design Page 10.8-7 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 EXAMPLE 10.8-2 Comparator Bandwidth Limitations on the Flash ADC The comparators of a 6-bit, flash ADC have a dominant pole at 103 radians/sec, a dc gain of 104 a slew rate of 3V/µs, and a binary output voltage of 1V and 0V. Assume that the conversion time is the time required for the comparator to go from its initial state to halfway to its final state. What is the maximum conversion rate of this ADC if VREF = 5V? Assume the resistor ladder is ideal. Solution: The output of the i-th comparator can be found by taking the inverse Laplace transform of, L -1Vout(s) = Ao(s/103) + 1·Vin*-VRis → vout(t) = Ao(1 - e-103t)(Vin* - VRi). The worst case occurs when Vin*-VRi = 0.5VLSB = VREF27 = 5128 ∴ 0.5V = 104(1 - e-103T)(5/128) → 645·104 = 1- e-103T or, e103T = 1 - 6450,000 = 0.99872 → T = 10-3 ln(1.00128) = 1.2808µs ∴ Maximum conversion rate = 11.2808µs = 0.781x106 samples/second Check the influence of the slew rate on this answer. SR = 3V/µs → ∆V∆T = 3V/µs → ∆V = 3V/µs(1.2808µs) = 3.84V > 1V Therefore, slew rate does not influence the maximum conversion rate.CMOS Analog IC Design Page 10.8-8 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 OTHER ERRORS OF THE PARALLEL ADC • Resistor string error - if current is drawn from the taps to the resistor string this will create a “bowing” effect on the voltage. This can be corrected by applying the correct voltage to various points of the resistor string. • Input common mode range of the comparators - the comparators at the top of the string must operate with the same performance as the comparators at the bottom of the string. • Kickback or flashback - influence of rapid transition changes occuring at the input of a comparator. Can be solved by using a preamplifier or buffer in front of the comparator. • Metastability - uncertainty of the comparator output causing the transition of the thermometer code to not be distinct.CMOS Analog IC Design Page 10.8-9 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 INTERPOLATING ANALOG-DIGITAL CONVERTERS A 3-bit interpolating ADC using a factor of 4 interpolation: Comments: • Loading of the input is reduced from 8 comparators to two amplifiers. • The outputs of the two amplifiers, V1 and V2, are interpolated through the resistor string and applied to the comparators. • Because of the amplification of the input amplifiers and a single threshold, the comparators can be simple and are often replaced by a latch. • If the dots in Fig. 10.8-4 are not equally spaced, INL and DNL will result.CMOS Analog IC Design Page 10.8-10 Chapter 10 - DA and AD Converters (6/4/01) © P.E. Allen, 2001 • The comparators no longer need a large ICMRCMOS Analog IC Design


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