New version page

A Silicon Single-Electron Transistor Memory

Upgrade to remove ads

This preview shows page 1 out of 3 pages.

Save
View Full Document
Premium Document
Do you want full access? Go Premium and unlock all 3 pages.
Access to all documents
Download any document
Ad free experience

Upgrade to remove ads
Unformatted text preview:

1500 K/ps. We performed the simulations on a mas-sively parallel computer (29), using a time step of 0.7fs, for a total time of ;30 ps.22. B. R. Eggen et al., Science 272, 87 (1996).23. T. Guo et al., J. Phys. Chem. 99, 10694 (1995).24.X. Blase, L. X. Benedict, E. L. Shirley, S. G. Louie, Phys.Rev. Lett. 72, 1878 (1994); J.-C. Charlier, Ph. Lambin,T. W. Ebbesen, Phys. Rev. B 54, R8377 (1996).25. The molecular axis was initially orthogonal to thenanotube axis and oriented along a line not includingthe latter.26. R. S. Wagner and W. C. Ellis, Appl. Phys. Lett. 4,89(1964).27. S. Seraphin, D. Zhou, J. Jiao, Microscop. Acta 3,64(1994).28. S. Nose´,Prog. Theor. Phys. Suppl. 103, 1 (1991).29. A. De Vita, A. Canning, R. Car, EPFL Supercomput.J. 6, 22 (1994).30. Supported in part through the Parallel ApplicationTechnology Program between the E´cole Polytech-nique Fe´de´ rale de Lausanne (EPFL) and Cray Re-search, and by the Swiss NSF (grant 20-39528.93).J.-C.C. was supported by the National Fund for Sci-entific Research of Belgium and by a Human Capitaland Mobility Grant of the European Union. X.B. wasfunded in part by the Communaute´ de Travail desAlpes Occidentales (CO-TRAO). We are grateful toM. Teschner for providing the graphics tools used inthe work and to A. Canning for his contribution to thedevelopment of the parallel code.29 August 1996; accepted 6 December 1996A Silicon Single-Electron Transistor MemoryOperating at Room TemperatureLingjie Guo, Effendi Leobandung, Stephen Y. Chou*A single-electron memory, in which a bit of information is stored by one electron, isdemonstrated at room temperature. The memory is a floating gate metal-oxide-semi-conductor transistor in silicon with a channel width (;10 nanometers) smaller than theDebye screening length of a single electron and a nanoscale polysilicon dot (;7 nano-meters by 7 nanometers) as the floating gate embedded between the channel and thecontrol gate. Storing one electron on the floating gate screens the entire channel fromthe potential on the control gate and leads to (i) a discrete shift in the threshold voltage,(ii) a staircase relation between the charging voltage and the shift, and (iii) a self-limitingcharging process. The structure and fabrication of the memory should be compatiblewith future ultralarge-scale integrated circuits.To increase the storage density of semi-conductor memories, the size of eachmemory cell must be reduced. A smallermemory cell also leads to faster speeds andlower power consumption. One of thewidely used nonvolatile semiconductormemories is the metal-oxide-semiconduc-tor (MOS) transistor that has a floatinggate between the channel and the controlgate. Information is represented by storingcharges on the floating gate. The informa-tion can be read by using the transistorbecause different amounts of charge onthe floating gate shift the threshold volt-age of the transistor differently. The ulti-mate limit in scaling down the floatinggate memory is to use one electron torepresent a bit, the so-called single elec-tron MOS memory (SEMM). To makesuch memory practical requires a properdesign of device structure, so that thevoltage for charging a single electron isdiscrete and well separated (as comparedto the noise level), as is the shift in thresh-old voltage caused by the storage of asingle electron.One of the two previous approaches toSEMM is to build the device in a tinypolysilicon strip (1). An electron percola-tion path in the strip forms the channel,and one of polysilicon grains near theconduction path acts as the floating gate.Such a structure intrinsically prevents pre-cise control of the channel size, floatinggate dimension, and tunnel barrier. Theother approach is to replace the floatinggate of conventional floating gate transis-tor memory with nanocrystal grains, whilekeeping the rest of the device unaltered(2). The size of the silicon nanocrystalsand the tunnel barriers intrinsically have abroad distribution. Both approaches in-tend to alleviate the challenges in nano-fabrication, but the statistical variations intheir structures lead to large fluctuationsin the shift of the threshold voltage and inthe charging voltage, making them unsuit-able for large-scale integration.Here we present a SEMM in crystallinesilicon that has a well-controlled dimen-sion. Charging a single electron to thefloating gate leads, at room temperature,to a quantized shift in threshold voltageand a staircase relation between the shiftand the charging voltage. Furthermore,the charging process is self-limited.There are two key features of ourSEMM (Fig. 1): (i) the channel width ofsilicon MOS field-effect transistor is nar-rower than the Debye screening length ofa single electron and (ii) the floating gateis a nanoscale square (hence, it is called adot) (3). Otherwise, the device is similarto an ordinary floating gate MOS memory.The narrow channel ensures that the stor-age of a single electron on the floatinggate is sufficient to screen the entire chan-nel (that is, the full channel width) fromthe potential on the control gate, whichleads to a significant shift in thresholdvoltage. A small floating gate is used tosignificantly increase electron quantumenergy (due to the small size) and electroncharging energy (due to the small capaci-tance); hence, the threshold voltage shiftand the charging voltage become discreteand well separated at room temperature.The control gate in our device is long, butthe device’s threshold is determined bythe section where the floating gate islocated.In fabrication, an 11-nm-thick polysili-con film (for the floating gate) was depos-ited on a silicon-on-insulator wafer that hada35-nm-thick top layer of crystalline sili-con (for the channel). The polysilicon filmand the silicon layer were separated by alayer of native oxide ;1 nm thick. The firstlevel of electron beam lithography (EBL)and reactive ion etching (RIE) patternedthe width of the floating gate and the nar-row silicon channel, which is under the gate(that is, they are self-aligned). The initialchannel width varied from 25 to 120 nm. Asecond level of EBL and RIE patterned thelength of the floating gate, making it square(Fig. 2). An 18-nm-thick layer of oxide wasthen thermally grown, partially consumingthe silicon, which reduced the thickness ofthe polysilicon dot by ;9 nm and the lat-eral size of the dot and the width of thesilicon channel by ;18 nm. A 22-nm-thicklayer of oxide was deposited by plasma-enhanced chemical vapor


Download A Silicon Single-Electron Transistor Memory
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view A Silicon Single-Electron Transistor Memory and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view A Silicon Single-Electron Transistor Memory 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?