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Parameterized Macromodeling for Analog System-Level Design Exploration

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Parameterized Macromodeling for Analog System-Level Design Exploration Jian Wang, Xin Li and Lawrence T. Pileggi Department of ECE, Carnegie Mellon University 5000 Forbes Ave, Pittsburgh, PA 15213, USA {jianw, xinli, pileggi}@ece.cmu.edu ABSTRACT In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our proposed approach captures a significantly larger analog design space to facilitate system-level design exploration. Combining a novel piece-wise approximation algorithm and a new multi-point model-order-reduction approach, the proposed method generates compact macromodels covering the entire feasible design space. Our experiments demonstrate that using such models can achieve more than 60× speed-up while incurring less than 4% overall error when varying design parameters by an order of magnitude. Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids – simulation General Terms: Algorithms, Design Keywords: Analog macromodeling, parameterized macromodel 1. INTRODUCTION As the complexity of on-chip analog systems continues to increase, designing and optimizing these large-size systems become increasingly challenging. One major difficulty of analog system optimization stems from the expensive performance evaluation, which requires SPICE simulation of large transistor-level netlists and is impractical to be included into an optimization loop. In order to make analog optimization computationally feasible, various modeling techniques have been proposed. One well-known approach is to approximate the block-level performance (e.g., amplifier gain) as a function of design variables [1–3]. However, a complete analog system (e.g., ADC, PLL) consists of dozens, or even hundreds of building blocks. Directly building the performance model for the entire system is too expensive, since it requires thousands or even millions of simulation samples [3]. Conversely, using block-level performance models to evaluate system-level performance is not easy, since the relation between block-level and system-level performances is typically unknown. In this paper, we propose to systematically create block-level parameterized macromodels that are suitable for analog system-level optimization. Our proposed macromodel attempts to approximate the input-output relationship of an analog block by a set of simplified differential algebraic equations. These block-level macromodels can be interconnected to facilitate fast system-level simulation. In addition, unlike traditional analog macromodels that have been mostly applied for bottom-up verification [1], the proposed macromodel is parameterized as a function of design variables such that it can facilitate top-down design exploration. To create such parameterized macromodels, the challenging problem is how to accurately capture a large design space where the design variables can vary by orders of magnitude. The author of [4] demonstrated that for most analog circuits, a number of implicit sizing rules must be enforced to guarantee circuit functionality. Therefore macromodels should be created over this constrained design space, or feasible region only. As we will demonstrate in this paper, a low-dimensional projection space can be found for parameterized order reduction, if and only if the analog circuit stays within its feasible region. The proposed analog macromodeling algorithm consists of two steps. Firstly, a novel algorithm is applied to automatically and recursively partition the large design space into small portions. The partitioning is formulated as a convex programming problem such that it can be solved both efficiently and robustly. Thereby a unified global macromodel is constructed as an accurate piece-wise approximation over the entire feasible region. Such a piece-wise approximation is necessary in our application, since most analog circuit equations are strongly nonlinear in feasible region and cannot be easily approximated by low-order polynomials. Next, parameterized order reduction is applied to create a simple, yet accurate macromodel. We extend the single-point multi-parameter moment matching proposed in [5–6] to multiple-point cases such that creating a unified macromodel over the large design space becomes feasible. 2. BACKGROUND 2.1 Feasible Region For analog design, after the circuit topology is decided, the designer will try to improve the performance of interest by optimizing several design variables, such as transistor sizes. In this paper, we assume that there are in total k design variables121],,,[×∈=kTkRpppp L. The space spanned by the design variables is referred to as the design space. In practice, a set of constraints must be applied to the design variables, which can be derived from physical requirements such as the minimal transistor size, or from functional requirements such as the bias condition for keeping a transistor in saturation [4]. These constraints generally can be approximated by posynomial functions in the form of [2]: Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC 2007, June 4–8, 2007, San Diego, California, USA Copyright 2007 ACM 978-1-59593-627-1/07/0006…$5.00 94050.3∑≤=ikikiippcpf 1)(11ααL (1) where ci is real non-negative and 121],,,[×∈=kTikiiiRααααL. A design satisfying all the constraints is considered functional. The design space defined by those constraints is referred to as the feasible region [4], denoted as }1 ,1)(|{ KjpfpPjL=≤=. 2.2 Parameterized Macromodel For simplicity we limit our discussion in this paper to linear time-invariant (LTI) macromodeling. However, it should be noted that the proposed methodology can be extended to weakly nonlinear and/or time-variant macromodeling with minor modification. In general, the LTI behavior of an analog circuit can be modeled by a set of linearized equations at the DC bias point: ()xLyBuxGsCT==+ (2) where 1×∈mRu , 1×∈lRy , 1×∈NRx ; C, G, B and LT are matrices with appropriate dimensions. For a particular


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