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Understanding Voltage Variations

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Understanding Voltage Variations in Chip Multiprocessorsusing a Distributed Power-Delivery NetworkMeeta S. Gupta∗, Jarod L. Oatley∗, Russ Joseph†, Gu-Yeon Wei∗and David M. Brooks∗∗Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA{meeta,jloatley,wei,dbrooks}@eecs.harvard.edu†Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, [email protected]— Recent efforts to address microprocessor powerdissipation through aggressive supply voltage scaling and powermanagement require that designers be increasingly cognizant ofpower supply variations. These variations, primarily due to fastchanges in supply current, can be attributed to architecturalgating events that reduce power dissipation. In order to studythis problem, we propose a fine-grain, parameterizable modelfor power-delivery networks that allows system designers tostudy localized, on-chip supply fluctuations in high-performancemicroprocessors. Using this model, we analyze voltage variationsin the context of next-generation chip-multiprocessor (CMP)architectures using both real applications and synthetic currenttraces. We find that the activity of distinct cores in CMPs presentseveral new design challenges when considering power supplynoise, and we describe potentially problematic activity sequencesthat are unique to CMP architectures.I. INTRODUCTIONSupply-voltage fluctuations have emerged as a serious causefor concern in high-performance processor design. These per-turbations occur when the processor demands rapidly changecurrent consumption over a relatively small time scale. Sincethe power-delivery subsystem can have substantial parasiticinductance, this current variation produces voltage ripple onthe chip’s supply lines. This is significant because if thesupply voltage rises or drops below a specific tolerance range,the CPU may malfunction. This fundamental challenge isknown as the dI/dt problem since the magnitude of thesevoltage ripples is affected by the instantaneous change ofcurrent with respect to time. Current fluctuations are primarilyderived from dynamic resource utilization fluctuations, whichare heavily influenced by architectural power-saving eventssuch as clock- and power-supply gating and idle/sleep modes.Thus, analysis at the architecture-level is critical to allow de-signers to understand the impact of these techniques on power-supply voltage stability under a variety of power-delivery andpackage-modeling assumptions.Previous architecture-level dI/dt studies ([1] and [2]) haveused lumped models of the on-chip power-delivery networkto capture the mid-frequency resonance. The major limitationof these architectural models is the global treatment of on-chip VDD/GND as single nodes, which fails to capture localon-die voltage variations across the chip. As the effects ofsupply variation play a more prominent role in performanceand reliability, architects will have to pay closer attentionto localized supply fluctuations due to package connectionsand the on-chip power-supply grid. In this paper, we describean architecture-level, fine-grained, power-delivery model thatcaptures localized voltage variations across the entire chip.Current technology trends are moving towards chip multi-processor (CMP) architectures like IBM’s Cell processor [3]and Intel’s Core Duo processor [4]. It is important to un-derstand inter-core voltage variations for multiple cores ona CMP machine. Core utilization patterns and activity in-teractions between cores can lead to large inter-core voltagevariations. In order to understand these inter-core variations,a fine-grained power-delivery network is needed to modelthese effects. Using a distributed power-delivery model of theon-chip power-supply grid, we explore the repercussions ofdifferent combinations of activity patterns.The main contributions of our work are:1) We provide a parameterizable, distributed, power-delivery model, which can be configured to closelymatch measured impedances found in the literature [5].2) This paper investigates voltage variations across a CMPmachine using both real and synthetic activity patterns.3) We illustrate possible problematic activity sequencesthat are unique to CMP architectures.The paper is organized as follows: Section II describesthe modeling of a distributed power-delivery network. Thedifferent types of activities and their effects on voltage vari-ations are studied in Section III. Section IV reviews priorresearch generally related to power delivery modeling. Finally,Section V concludes the paper.II. MODELING THE POWER DELIVERY NETWORKThis section presents a detailed yet flexible power-deliverymodel that captures the characteristic mid-frequency reso-nance, transients related to board and package interfaces, andlocalized on-chip voltage variations.Figure 1(a) presents our detailed model of the power-delivery network with a distributed on-chip power-supplygrid. The off-chip network includes the motherboard, package,and off-chip decoupling capacitors and parasitic inductances,modeled via a ladder RLC network. Figure 1(b) illustratesthe distributed on-chip grid model used in our analysis. TheC4 bumps are modeled as parallel connections (via RL pairs)that connect the grid to the off-chip network, with each grid(a) Package model (b) On-die grid modelFig. 1. Power delivery model10510610710810901234567Frequency (Hz)Impedance (mOhm)Off−Chip Impedance Plot Lumped ModelDistributed Model(a) Off-chip1051061071081090123456789Frequency (Hz)Impedance (mOhm)On−chip Impedance Plot Lumped ModelDistributed Model(b) OnChipFig. 2. Off-chip and on-die impedance plotspoint having a bump connection. The on-chip grid itself ismodeled as an RL network. The evenly distributed on-chipcapacitance between the VDD and GND grids is modeledin two ways — Cspcrepresents the decoupling capacitanceplaced in the free space between functional units and Cblkrepresents the intrinsic parasitic capacitance of the functionalunits. In contrast, an on-chip lumped model would consistof a single RLC network connected across the package-to-chip interface. Table I provides the values of the resistances,inductances, and capacitances used for the PCB, package andon the die, for the lumped and distributed power-deliverymodels. These values were chosen to match the measured off-chip impedance of the Pentium 4 processor [5], [6]. Figure 2(a)plots the off-chip impedance for the lumped


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