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Self-Heating Enhanced Impact Ionization in SO1 MOSFETs

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31 200 1 IEEE International SO1 Conference, IO/O I Self-Heating Enhanced Impact Ionization in SO1 MOSFETs P. Su, K. Goto", T. Sugii" and C. Hu Department of EECS, U. C. Berkeley, Berkeley, CA94720, USA "Fujitsu Laboratory Ltd., 10- 1 Morinosato- Wakamiya, Atsugi 243-0197, Japan Email: [email protected] Tel: (510) 643-2637 Introduction Impact ionization (II) originates from energetic carrier in the channel. The 11 current is not only a monitor of device reliability, but also affects the current drive of partially-depleted (PD) SO1 transistors by charging up the floating body and hence varying the threshold voltage. Due to the low thermal conductivity of buried oxide, SO1 MOSFETs are susceptible to the local thermal heating generated in the channel. This SOI-specific self-heating effect (SHE) provides a source for camer heating, which may determine impact ionization. In this paper we report an enhanced impact-ionization phenomenon caused by SHE in SO1 MOSFETs. Devices Co-processed bulk and PD SO1 MOSFETs using a 0.13pm technology [I] are investigated. The nominal device with a 0. lpm design length has a 50nm effective channel length. For SOI, the thicknesses of the gate oxide, silicon film and buried oxide are 2.8nm, lOOnm and 360nm. respectively. Results and Discussion Fig. 1 shows that the 11 current in the SO1 transistor is larger than the bulk counterpart at high gate bias (V,). The II rate defined as the ratio of the II current to the drain current, I&, can be used to understand the underlying mechanism. As shown in Fig. 2, the identical I1 rate at low V, demonstrates that the co- processed bulk and SO1 samples are nearly identical. As V, increases, however, the II rate of the SO1 transistor becomes larger than the bulk one. As V, increases. the power and therefore the device temperature of the SO1 MOSFET rises due to self- heating. The increase of the II rate with temperature [3][3] shown in Fig. 3 explains the phenomenon observed in Fig. 1 and Fig. 2. Notice that for a given high V,, this I1 enhancement due to SHE does not decrease with the drain bias (V,) because of the higher temperature sensitivity of the 11 rate at the lower V, as shown in Fig. 3. Since a larger current drive gives bigger power consumption and hence higher temperature rise, the I1 enhancement is more significant for the SO1 transistor with shorter channel length as shown in Fig. 4. For a given bias and substrate temperature (To), the SO1 device temperature and thus the temperature rise (AT) can be projected by finding the corresponding temperature which gives the same amount of II rate in the bulk device as illustrated in Fig. 4. The fact that the extracted ATJAT? equals to the measured ID~ID~ demonstrates the self-heating enhanced impact ionization quantitatively. The SHE enhanced I1 current present in the dc measurement of Fig. 1 will be absent in most logic circuits. Since the average power consumption per device is low and its switching time (-lops) is much shorter than the thermal time constant (- 1 OOns). the time-averaged and transient device-temperature rises due to SHE are quite small [4]. Therefore, the SHE-free II data shown in Fig. 5 should be used and modeled for accurate logic circuit simulation. It can be obtained by calculating the device temperature (To + power x thermal resistance) and measuring the temperature dependence of the I1 current. Likewise, the device dynamic lifetime will be underestimated when extrapolated from static II data due to this effect. Conclusion We report a self-heating enhanced impact-ionization phenomenon in SO1 MOSFETs. Since the I1 rate is larger at higher temperature under low supply drain voltages (below 2V) [3], more I1 current is induced for the SO1 transistor at high gate dc bias. The effect should be modeled for circuit simulation. Acknowledgement This work is supported by the SRC under contract 2OOO-SJ-795. 0-7803-6739- 110 11s 10.00 0200 1 IEEE32 2001 IEEE international SO1 Conference, 10/01 1 O'lC Figure 1. Larger impact ionization current is observed for the SO1 transistor at high gate bias. 1 O'I v,, (V) Figure 2. The I1 ratc of the SO1 MOSFET is larger than thc hulk counterpart at high gate bias. even though the two transistors arc ncarly identical. 10" :o" substrate temperature ("C) Figure 3. The I1 rate increases as tcmperature rises. This explains the SHE cnhanccd impact ionization occurring at high gate bias and thus high dcvice temperature. Notice that the lower the drain vottage. the higher temperature sensitivity of the 11 rate. 30 60 90 substrate tern perature ("C) Figure 4. The I1 enhancement is more pronounced for shortcr channel length. The SO1 temperature rise (AT) can be extracted by the I& data and shown to be proportional to ID. It verifies quantitatively the SHE enhanced I1 effect. -0- self-heatingtree data NFET SO1 2.50X10" 0.3 0.6 0.9 1.2 1 5 v,, tV) Figure 5. The SO1 device temperature can be calculated and used to zet the SHE-free 11 data. which should be modeled for logic circuit simulation. Notice that the long-channel bell-shapc characteristic is no longer present for the NMOSFET with 50nm cffective channel length. Reference [ 1 Y. Momiyama et al., IEDM Tech. Dig., p.45 1.2OOO. 121 M. Mastrapasqua et al., VLSI Symp.. p. 125, 1994. 131 N. San0 ct al., IEEE TED, vol. 42, no. 12, Dec 1995. [4] H. Nakayama et al., CICC Tech. Dig..


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