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UW-Madison PHYSICS 623 - ISE In-Depth Tutorial

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ISE In-Depth TutorialAbout This TutorialAbout the In-Depth TutorialTutorial ContentsTutorial FlowsHDL Design FlowSchematic Design FlowImplementation-only FlowAdditional ResourcesTable of ContentsOverview of ISE and Synthesis ToolsOverview of ISEProject Navigator InterfaceSources WindowProcesses WindowTranscript WindowWorkspaceUsing Revision Control FeaturesUsing SnapshotsUsing Project ArchivesUsing Export/Import Source ControlOverview of Synthesis ToolsPrecision SynthesisSynplify/Synplify ProXilinx Synthesis Technology (XST)HDL-Based DesignOverview of HDL-Based DesignGetting StartedRequired SoftwareOptional Software RequirementsVHDL or Verilog?Installing the Tutorial Project FilesStarting the ISE SoftwareCreating a New ProjectStopping the TutorialDesign DescriptionInputsOutputsFunctional BlocksDesign EntryAdding Source FilesChecking the SyntaxCorrecting HDL ErrorsCreating an HDL-Based ModuleCreating a CORE Generator ModuleCreating a DCM ModuleSynthesizing the DesignSynthesizing the Design using XSTSynthesizing the Design using Synplify/Synplify ProSynthesizing the Design Using Precision SynthesisSchematic-Based DesignOverview of Schematic-Based DesignGetting StartedRequired SoftwareInstalling the Tutorial Project FilesStarting the ISE SoftwareCreating a New ProjectStopping the TutorialDesign DescriptionInputsOutputsFunctional BlocksDesign EntryOpening the Schematic File in the Xilinx Schematic EditorManipulating the Window ViewCreating a Schematic-Based MacroDefining the time_cnt SchematicCreating and Placing the time_cnt SymbolCreating a CORE Generator ModuleCreating a State Machine ModuleCreating the State Machine SymbolCreating a DCM ModuleCreating the dcm1 SymbolCreating an HDL-Based ModuleCreating the debounce SymbolPlacing the statmach, timer_preset, dcm1 and debounce SymbolsChanging Instance NamesHierarchy Push/PopSpecifying Device Inputs/OutputsAssigning Pin LocationsCompleting the SchematicBehavioral SimulationOverview of Behavioral Simulation FlowModelSim SetupModelSim PE and SEModelSim Xilinx EditionISE Simulator SetupGetting StartedRequired FilesXilinx Simulation LibrariesAdding an HDL Test BenchAdding Tutorial Test Bench FileBehavioral Simulation Using ModelSimLocating the Simulation ProcessesSpecifying Simulation PropertiesPerforming SimulationAdding SignalsSaving the SimulationBehavioral Simulation Using ISE SimulatorLocating the Simulation ProcessesSpecifying Simulation PropertiesPerforming SimulationAdding SignalsRerunning SimulationCreating a Test Bench Waveform Using the Waveform EditorDesign ImplementationOverview of Design ImplementationGetting StartedContinuing from Design EntryStarting from Design ImplementationSpecifying OptionsCreating PartitionsCreating Timing ConstraintsTranslating the DesignUsing the Constraints EditorUsing the Floorplan EditorMapping the DesignUsing Timing Analysis to Evaluate Block Delays After MappingEstimating Timing Goals with the 50/50 RuleReport Paths in Timing Constraints OptionPlacing and Routing the DesignUsing FPGA Editor to Verify the Place and RouteEvaluating Post-Layout TimingChanging HDL with PartitionCreating Configuration DataCreating a PROM File with iMPACTCommand Line ImplementationTiming SimulationOverview of Timing Simulation FlowGetting StartedRequired SoftwareRequired FilesSpecifying a SimulatorTiming Simulation Using ModelSimSpecifying Simulation Process PropertiesPerforming SimulationTiming Simulation Using Xilinx ISE SimulatorSpecifying Simulation Process PropertiesPerforming SimulationiMPACT TutorialDevice SupportDownload Cable SupportParallel Cable IVPlatform Cable USBMultiPRO CableConfiguration Mode SupportGetting StartedGenerating the Configuration FilesConnecting the CableStarting the SoftwareCreating a iMPACT New Project FileUsing Boundary Scan Configuration ModeSpecifying Boundary Scan Configuration ModeAssigning Configuration FilesSaving the Project FileEditing PreferencesPerforming Boundary Scan OperationsTroubleshooting Boundary Scan ConfigurationVerifying Cable ConnectionVerifying Chain SetupCreating an SVF FileSetting up Boundary Scan ChainWriting to the SVF FileStop Writing to the SVFPlaying back the SVF or XSVF fileOther Configuration ModesSlave Serial Configuration ModeSelectMAP Configuration ModeRISE In-DepthTutorial10.1ISE 10.1 In-Depth Tutorial www.xilinx.comXilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operateon, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished,downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical,photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyrightlaws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes noobligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for theaccuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION ISWITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION ORADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHEREXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESSFOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOUHAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTIONWITH YOUR USE


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