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Modeling OPC Complexity

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Modeling OPC Complexity for Design for ManufacturabilityPuneet Guptaa, Andrew B. Kahnga,b,c, Sw amy Mudduc, Sam Nakagawaaand Chul-HongParkcaBlaze DFM Inc, Sunnyvale CA, USA 94089bCSE Department, UCSD, La Jolla CA, USA 92093cECE Department, UCSD, La Jolla CA, USA 92037ABSTRACTIncreasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolutionenhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressiveoptical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexityand cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Maskcost is determined by mask write time and mask inspection time, which are directly related to the complexity offeatures printed on the mask. Aggressive RET increase complexity by adding assist features and by modifyingexisting features.Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost inseveral recent works2,3,4. The goal of design-aware OPC is to relax OPC tolerances of layout features tominimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing,design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires.Design optimization should be aware of impact of OPC correction levels on mask cost and performance of thedesign. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured interms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is acritical step in linking design and manufacturing.In this paper, we present a MCC methodology that provides models of fracture count of standard cells andwire patterns for use in design optimization. MCC cannot be performed by designers as they do not have accessto foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on alimited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify thecharacteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC andmask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.Keywords: OPC, Fracturing, Mask cost, DFM1. INTRODUCTIONRET such as assist feature insertion and OPC are mandatory post tapeout steps to ensure printability of featuresin sub-90nm technology nodes. Doubling of layout data volume every technology node combined with aggressiveRET is driving mask set cost to prohibitive levels. Transferring design intent to OPC process can reduce theincreasing complexity of masks in sub-90nm technology nodes. Design intent-aware OPC applies different levelsof OPC correction to different regions of a design based on their criticality.There are two approaches for minimizing mask cost using design information. In the first approach, timingand power analysis are performed on the design to identify all critical paths and their corresponding layoutfeatures. OPC is then performed with tight tolerances on all critical features and with relaxed tolerances on allnon-critical features to minimize mask cost. This approach (e.g., Cote et.al2)doesnotmodifythedesignflowprior to the tapeout. However, relaxing OPC tolerance uniformly on all non-critical features does not lead tothe best possible mask cost reductions. In the second approach, tolerance optimization is performed by choosingOPC tolerance combination specific to the standard cell or wire pattern by analyzing its impact on mask costand design performance simultaneously. Gupta et.al.3propose such an approach for minimizing mask cost byrelaxing OPC tolerances on standard cells, subject to meeting timing constraints . In this flow, OPC toleranceoptimization is performed prior to tapeout.25th Annual BACUS Symposium on Photomask Technology, edited by J. Tracy Weed, Patrick M. Martin,Proc. of SPIE Vol. 5992, 59921W, (2005) · 0277-786X/05/$15 · doi: 10.1117/12.633416Proc. of SPIE Vol. 5992 59921W-1Characterization of mask cost and timing impact of different OPC tolerances is the basic step for a completedesign-aware OPC flow. In this work, we characterize mask cost of standard cells and wires without performingOPC repeatedly with different tolerances. Based on the statistical analysis of FC of standard cell and wirepatterns, we construct models and lookup tables of mask cost that can be used for OPC tolerance optimization.For standard cells, we give models of mask cost of polysilicon layer with inner tolerance (IT), outer tolerance(OT), starting side (SSIDE) and fragmentation edgelength (FRAG) of feature edges in the layout. Designengineers can perform trade-offs between parametric yield and mask cost using this model. RET engineers canuse the model of mask cost to tune their OPC recipes without running OPC and fracturing. Since the modelprovides mask cost as a function of layout parameters, library designers can modify device layout to minimizemask cost without running OPC and fracturing repeatedly. Further, MCC can be used to drive mask-friendlylayout optimizations that can potentially improve yield.OPC adjusts edge placement of features in the layout according to tolerance combination within the specifiednumber of iterations. In addition to tolerance combination, the final fracture count of an OPC’ed layout dependson the convergence criterion of the OPC algorithm and the edgelength of fragments. Since OPC algorithm isiterative, modeling edge placement of features and fracture count is very difficult. Instead, we model the responseof the OPC algorithm as a function of OPC tolerances and layout parameters. Layout dimensions and geometriesof devices in standard cells is different from that of wires. Hence, we perform MCC for standard cells and wiresdifferently.To build mask cost models, we assume that fracture counts are generated with sign-off OPC recipes andoptical models. Unless otherwise mentioned, fracture count of a standard cell refers to the fracture count ofpolysilicon (poly) layer only. In this work, we do not consider assist feature insertion during MCC. This paperis organized as follows. In Section 2 we present MCC methodology for standard cells. In Section 3 we presentMCC methodology for wires. Layout styles and properties for standard cells


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