Course AdministrationSlide 3ConventionCourse Goals and Structurespim Assembler and Simulatorvhdl Analyzer and SimulatorGrading InformationGrading PoliciesAbout 14:332:333Head’s UpWhat You Should Already KnowSlide 14Advantages of Higher-Level LanguagesMajor Components of a ComputerComputer TypesComputer OrganizationInstruction vs. DataInput Device Inputs Object CodeObject Code Stored in MemoryMemory Unit: to store the programHow to execute a program?Processor OrganizationInstruction FetchProcessor Fetches an InstructionControl Decodes the InstructionDatapath Executes the InstructionOutput Data Stored in MemoryOutput Device Outputs DataHardware/Software InterfaceThe Instruction Set ArchitectureMIPS R3000 Instruction Set ArchitectureHow Do the Pieces Fit Together?Slide 36331 W01.2Spring 2006Course AdministrationInstructor: Yanyong Zhang [email protected]Core 518Hours: TF 10:30 –11:30 amTAs: TBD Labs: Everyone will be using your ece account. Texts:Computer Organization and Design: The Computer Organization and Design: The Hardware/Software Interface, Hardware/Software Interface, Third EditionThird Edition, , Patterson and HennessyPatterson and Hennessy VHDL Starter’s GuideVHDL Starter’s Guide, Yalamanchili, Yalamanchili331 W01.3Spring 2006Course AdministrationCourse web page http://www.ece.rutgers.edu/~yyzhang/spring06 Please check the course web page regularly (at least once before class) for announcements, assignments, and more importantly, lecture notes.Class mailing list [email protected] By default, I will use your eden account. If you prefer another email account, please send me emails.Please post emails on this list only when you want to talk to the whole class. If you only want to talk to the instructor, or a TA, please send him/her individual emails. I will be using the list to distribute the announcements and answer some common questions.I will send test messages before Friday’s lecture. Please talk to me on Friday if you haven’t got anything.WebCT is available for you to check your grades and conduct group discussion. Please do not expect the instructor to participate.331 W01.4Spring 2006ConventionPlease check your email and the course web page regularly.Every classFirst 10-15 minutes, review of last class Students will be randomly picked to answer questionsClass participation will be based on thisDiscussion-orientedInstructor vs. TA vs. studentsInstructors are responsible for answering questions related to the lectures and examsTAs are responsible for answering questions related to homework, projects, and gradesIf TAs cannot answer the students, they will contact the instructor directly.331 W01.5Spring 2006Course Goals and StructureFundamentals of assembly language programmingMIPS assembler programming using the spim systemIntroduction to the major components of a computer system. To bridge the gap between high level programming and low level digital design. VHDL design simulation using the Synopsys VSS toolsPrerequisite (required): 14:332:231 Digital Logic Design14:332:252 Programming Methodology Corequisites14:332:333 Computer Architecture Lab331 W01.6Spring 2006spim Assembler and Simulatorspim is a self-contained assembler and simulator for the MIPS R2000/R3000It provides a simple assembler, debugger and a simple set of operating system servicesIt implements both a simple, terminal-style interface and a visual windowing interfaceAvailable asxspim on unix-installed on the Sun machines in EE bldg, /usr/local/spim/bin/xspim PCSpim on Windows-can be downloaded and installed on your own PC from www.cs.wisc.edu/~larus/spim.html Sorry, there is no Macintosh version of spim331 W01.7Spring 2006vhdl Analyzer and SimulatorVSS is Synopsys’s VHDL system simulatorIt provides a vhdl analyzer that translates vhdl code into the binary required by the vhdl simulatorIt provides a vhdl simulator and a source code debugger with a graphical user interface for monitoring the simulationIt provides a waveform viewer for observing the results of the simulation as signal waveformsAvailable asvhdlan (text based) or gvan (graphical)vhdlsim (text based) or vhdldbx (graphical)waves-The entire (almost) Synopsys tool set is installed on the Sun machines in the EE bldg331 W01.8Spring 2006Grading InformationGrade determinatesMidterm Exam #1 ~21%Midterm Exam #2 ~23%Final Exam ~26%Homework Assignments ~20%In-class pop quizzes ~ 5%Class Participation ~ 5%Please let me know about exam conflicts ASAP331 W01.9Spring 2006Grading PoliciesAssignments will be submitted via email (mostly) and must be turned in by 5:00pm on the due date. No late assignments will be accepted.All the assignments should be completed individually. Duplicate assignments will receive duplicate grades of zero. Second offenses will result in a final course grade of F.Grades will be posted on the WebCTSee TAs about grading questions on the assignments; see instructor (me) about grading questions on the exams331 W01.10Spring 2006About 14:332:33314:332:333 will start from the week of 1/30 (the week after next)Enrollment:Section: 01 Time: M 12:00-3:00 PM 12Section: 02 Time: M 3:20-6:20 PM 8Section: 04 Time: W 12:00-3:00 PM 17Section: 05 Time: W 3:20-6:20 PM 4Section: 07 Time: F 3:20-6:20 PM 6I would like to cancel Sections 05 and 07.331 W01.11Spring 2006Head’s UpThis week’s materialCourse introduction-Reading assignment – PH 1.1 through 1.3 and A.9 through A.10Reminders14:332:333 will start from next weekQuestion/comments about the system go to [email protected]; questions about the programming assignments go to the course TAs.Next week’s materialIntroduction to MIPS assembler-Reading assignment - PH 3.1 through 3.3, 3.4, and 3.7331 W01.12Spring 2006What You Should Already KnowHow to write, compile and run programs in a higher level language (C, C++, Java, …)How to create, organize, and edit files and run programs on UnixHow to represent and operate on positive and negative numbers in binary form (two’s complement, sign magnitude, etc.)Logic designHow to design combinational and sequential components (Boolean algebra, logic minimization, technology mapping, decoders and multiplexors, latches and flipflops,