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UH COSC 6385 - Instruction Set Architectures

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COSC 6385 Computer Architecture Instruction Set Architectures Edgar Gabriel Spring 2012 Edgar Gabriel Instruction Set Architecture ISA Definition on Wikipedia Part of the Computer Architecture related to programming Defines set of operations instruction format hardware supported data types named storage addressing modes sequencing Includes a specification of the set of opcodes machine language native commands implemented by a particular CPU design COSC 6385 Computer Architecture Edgar Gabriel 1 Instruction Set Architecture II ISA to be distinguished from the micro architecture set of processor design techniques used to implement an ISA Example Intel Pentium and AMD Athlon support a nearly identical ISA but have completely different micro architecture COSC 6385 Computer Architecture Edgar Gabriel ISA Specification Relevant features for distinguishing ISA s Internal storage Memory addressing Type and size of operands Operations Instructions for Flow Control Encoding of the IS COSC 6385 Computer Architecture Edgar Gabriel 2 Internal storage Stack architecture operands are implicitly on the top of the stack Accumulator architecture one operand is implicitly the accumulator General purpose register architectures operands have to be made available by explicit load operations Dominant form in today s systems COSC 6385 Computer Architecture Edgar Gabriel Internal storage II Example C A B Stack Push A Push B Add Pop C Accumulator Load A Add B Store C Load Store Load R1 A Load R2 B Add R3 R1 R2 Store R3 C COSC 6385 Computer Architecture Edgar Gabriel 3 Internal storage III Advantage of general purpose register architectures vs stack architectures Registers are fast Easier and faster to evaluate complex expressions e g A B B C A D Registers can hold temporary variables Reduces memory traffic A register can be named with fewer bits than main memory COSC 6385 Computer Architecture Edgar Gabriel Addressing modes How does an ISA specify the address an object will access Addressing mode Example instruction Meaning Register Add R4 R3 Regs R4 Regs R4 Regs R3 Immediate Add R4 3 Regs R4 Regs R4 3 Register indirect Add R4 R1 Regs R4 Regs R4 Mem Regs R1 Displacement Add R4 100 R1 Regs R4 Regs R4 Mem 100 Regs R1 Memory indirect Add R4 R3 Regs R4 Regs R4 Mem Mem Regs R3 COSC 6385 Computer Architecture Edgar Gabriel 4 Addressing modes II Addressing modes must match Ability of compilers to use them Hardware characteristics Which modes are most commonly used Displacement Immediate Register indirect Size of address for displacement mode Typically 12 16 bits Size of the immediate field 8 16 bits COSC 6385 Computer Architecture Edgar Gabriel Internal storage IV Two major GPR architectures 2 or 3 operands for ALU instructions 3 operands 2 source 1 result 2 operands 1 operand is both source and result How many operands can be memory addresses No of memory addresses Max no of operands Architecture 0 3 Register register load store arch 1 2 Register memory 2 2 Memory memory 3 Memory memory 3 COSC 6385 Computer Architecture Edgar Gabriel 5 Memory alignment I Memory is typically aligned on a multiple of word boundaries Best case accessing misaligned address leads to performance problems since it requires accessing multiple words Worst case hardware does not allow misaligned access COSC 6385 Computer Architecture Edgar Gabriel Memory alignment II Width of object 0 1 2 3 4 5 6 7 1 byte A A A A A A A A 2 bytes half word A A 2 bytes half word M 4 bytes word A 4 bytes word 4 bytes word A M 8 bytes double word 8 bytes double word 8 bytes double word 8 bytes double word 8 bytes double word 8 bytes double word 8 bytes double word M A M M M M 4 bytes word 8 bytes double word A M M M A M M M M M M M COSC 6385 Computer Architecture Edgar Gabriel 6 Type and size of operands I How is the type of an operand designated Encoded in the opcode Annotated by tags Common operand types Character Half word Word Single precision floating point Double precision floating point 8bits 16 bits 32 bits 32 bits 64 bits 2 bytes 4 bytes 4 bytes 8 bytes COSC 6385 Computer Architecture Edgar Gabriel Type and size of operands II Encoding of characters ASCII UNICODE Encoding of integers Two s complement binary numbers Encoding of floating point numbers IEEE standard 754 No uniform representation of the data type long double COSC 6385 Computer Architecture Edgar Gabriel 7 Operations in the Instruction Set Operator type Examples Arithmetic and logical Integer arithmetic add subtract and or multiple divide Data transfer Load store move Control Branch jump procedure call return traps System OS call virtual memory management Floating point Floating point arithmetic add multiply divide compare Decimal Decimal add multiply String String move string compare string search Graphics Pixel and vertex operations compression COSC 6385 Computer Architecture Edgar Gabriel Flow Control instructions Four types of different control flow changes Conditional branches Jumps Procedure calls Procedure returns How to specify the destination address of a flow control instruction PC relative Displacement to the program counter PC Register indirect name a register containing the target address COSC 6385 Computer Architecture Edgar Gabriel 8 Flow Control instructions II Register indirect jumps also required for Case switch statements Virtual functions in C Function pointers in C Dynamic shared libraries dll in Windows so in UNIX Procedure invocation global variables could be accessed by multiple routines location of the variable needs to be known Options for saving registers Caller saving Callee saving due to the possibility of separate compilation many compilers store any global variable that may be accessed during a call COSC 6385 Computer Architecture Edgar Gabriel Encoding an Instruction Set How are instructions encoded into a binary representation Affects size of compiled program Affects implementation of the processor Decision depends on range of addressing modes supported Operation and Address Address Address Variable encoding no of operands specifier 1 field 1 specifier 2 Individual instructions can vary widely in size and amount of work to be performed Fixed encoding Operation Address Address field 1 field 2 Easy to decode Address field 2 COSC 6385 Computer Architecture Edgar Gabriel 9 Example Architecture MIPS64 I Load store architecture 32 64bit GPR registers R0 R1 R31 R0 contains always 0 32 64bit floating point registers F0 F1 F31 When using 32bit floating point


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