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MASON ECE 646 - Implementing Elementary Operations of Elliptic Cryptosystems in Hardware

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Additional LibrariesI/O SpecificationInvCircuit Functions and AlgorithmsProcedures For Testing FunctionalityPlan of Simulation Experiments On CircuitsTime SchedulePossible Areas of Specification ChangeList of LiteratureImplementing Elementary Operations of Elliptic Cryptosystems in Hardware By Ron Sulpizio Target Entry Method 1. The design entry method is VHDL. The target implementation will be a Xilinx FPGA. CAD tools used will be Active-HDL for preparing VHDL code and Synplicity Synplify Pro 7.2 for VHDL synthesis. After synthesis, Xilinx vendor tools will be used to program a FPGA. Additional Libraries 2. Additional library of basic digital circuits required in the design is Xilinx LogicBlox. I/O Specification 3. Multiplication Inputs: a.) N-bit A Multiplier b.) N-bit B Multiplicand Output: N-Bit result; where C=A*B over GF(2n). Square Inputs: a.) N-bit A Output: N-Bit result; where C=A2 Inv Inputs: a.) N-bit A Output: a.) N-bit result; where C=A-1 Circuit Functions and Algorithms 4. In computing kP in an elliptic curve cryptographic algorithm over GF(2N), two medium functions are used (P+Q and 2P). In computing P+Q and 2P, special multiplication (MUL), inversion (INV), and squaring (SQR) algorithms are needed. Multiplication For multiplication, several algorithms will be considered. The first algorithm is shown below:Other approaches will be considered as the result of continuing research. Inversion and Squaring Approaches still under consideration. Procedures For Testing Functionality 5. Procedures for testing the functionality and performance of the circuit(s) at the gate level, including a. The simulator in use will be Active HDL. b. The source of test vectors will be generated by me will be implemented in a VHDL test bench. c. The format of input stimuli will be a VHDL test bench and an input file into a FPGA chip d. Performance parameters to be determined by simulation is the number of d-bits that can be processed during multiplication, inverting, and squaring operations in one clock cycle on a 100 Mhz FPGA. e. Parameters to be determined using the implementation tools include number of CLBs in the FPGA implementation, minimum size FPGA device able to hold the device, and area of the circuit in the standard-cell implementation. Plan of Simulation Experiments On Circuits 6. Plan of simulation experiments to be performed using the circuit(s). • Develop correctly functioning VHDL code for Multiplier, Inverter, and Squarer. • Synthesize VHDL code using Synplicity Pro. • Test functionality of synthesized VHDL code with timing constraints on Multiplier, Inverter, and Squarer. • Test functionality of synthesized bit stream for Multiplier, Inverter, and Squarer. • Timing analysis of generated bit stream for Multiplier, Inverter, and Squarer. Time Schedule 7. Time schedule, including intermediate goals to be achieved by the dates of progress reports are shown below: October 13 -- Intermediate Goals for Completion by First Progress Report. • Define project • Research specifications and approaches to Multiplication, Inversion and Squaring. • Complete project specification report.• Chose Multiplication, Inversion, and Squaring algorithms to implement. • Begin implementation of Multiplier, Inverter, and Squarer in VHDL. November 3 -- Intermediate Goals for Completion by Second Progress Report. • Complete implementation of Multiplier, Inverter, and Squarer in VHDL. November 17 -- Intermediate Goals for Completion by Third Progress Report. • Complete simulation of Multiplier, Inverter, and Squarer. December 1 -- Intermediate Goals for Completion by Third Progress Report. • Prepare draft presentation Possible Areas of Specification Change 8. Possible areas, where the specification can change depending on the progress of the project include the amount of simulation actually occurs. The multiplier may take up all the time to the detriment of the Inverter and Squarer objectives. Also implementation of the Multiplier, Inverter, and Squarer could slip until the November 17 progress report depending on the complexity of problems that may arise. List of Literature 1. F. Rodriguez-Henriquez, “New algorithms and architectures for arithmetic in GF(2m) suitable for elliptic curve cryptography,” Ph.D. presentation, Dept. Elect. & Comp. Eng., Oregon State Univ., Corvallis, OR., presented on June 07, 2000. Available: http://islab.oregonstate.edu/papers/00Rodriguez.pdf 2. J. Guajardo and C. Paar, “Effcient algorithms for elliptic curve cryptosystems,” In B. S. Kaliski Jr., editor, Advances in Cryptology -- CRYPTO 97, Lecture Notes in Computer Science, No. 1294, pp. 342-356. Springer-Verlag, Berlin, Germany, 1997. 3. S. T. J. Fenn, M. Benaissa, and D. Taylor, “GF(2m) Multiplication and division over the dual basis,” IEEE Transactions on Computers, 45(3), pp. 319- 327, March 1996. 4. J. Lopez and R. Dahab. “Fast multiplication on elliptic curves over GF(2m) without precomputation,” In C. K. Koc and C. Paar, editors, Cryptographic Hardware and Embedded Systems, Lecture Notes in Computer Science, No. 1717, pp. 316-327. Springer-Verlag, Berlin, Germany, 1999.5. B. Ansari, “Achitecture for a fast elliptic curve co-processor - VLSI lab seminar,” Dr. H. Wu, Supervisor, Research Centre for Integrated Microsystems, University of Windsor, Windsor, Ontario. March 2004. Available: http://www.vlsi.uwindsor.ca/presentations/ansari4_seminar_1.pdf 6. G. Orlando and C. Paar, “A high-performance reconfigurable elliptic curve processor for GF(2m),” Computer Hardware and Embeddeed Systems, Lecture Notes in Computer Science, No. 1965, pages 41-56. Springer-Verlag, Berlin, Germany, 2000. Available: http://www.crypto.ruhr-uni-bochum.de/imperia/md/content/texte/orlandopaarches2000.pdf 7. A. Woodbury, “Efficient algorithms for elliptic curve cryptosystems on embedded systems,” M.S. thesis, Dept. Elec. Eng., Worchester Polytechnic Institute, Worchester, MA, September 2001. Available: http://www.wpi.edu/Pubs/ETD/Available/etd-1001101-195321/unrestricted/woodbury.pdf 8. L. Gao, S. Shrivastava, and G. Sobelman, “Elliptic curve scalar multiplier design


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