T. H. Lee Handout #14: EE214 Fall 2001 STANFORD UNIVERSITY Department of Electrical EngineeringFall Quarter, 2001 Midterm Design Problem Due: 21 Nov. 2001________________________________________________________________________ READ THIS ENTIRE HANDOUT THOROUGHLY! Op-amps are a widely useful (and widely used) analog building block, both as stand-alone chips, and as cells within larger integrated circuits. Undaunted by the recent downturn in the tech sector, you bravely choose to start an analog design house called Analog CMOS Module Engineering. A Diet Coke  overdose leads you to believe that ACME’s first product should be an op-amp capable of operation with a single supply voltage of 5V (the standard value for older TTL digital circuits). You also decide that the op-amp should meet the following specifications:|voltage gain|: as much in excess of 1000 as you can achieve (open-loop, low-fre-quency, small-signal, and over input common-mode values ranging from 0V to +3.5V); measured as the ratio of single-ended output voltage to differential input voltage at CM output voltage = 2.5V.Small-signal bandwidth: > 7MHz; measured in a follower configuration at 2.5V CM.Output swing within 250mV of both supply rails (measured at 2.5V input CM). Here, we’ll define “swing” as where the s.s. gain has dropped to 1000.On-chip capacitance of no more than 10pF.Load capacitance = 0.5pF; there is no external load resistance to worry about.Phase margin in follower configuration with specified load connected: > 50 ° .Maximum quiescent power of 5mW (measured at 2.5V output voltage and 2.5V input CM).Low-frequency CMRR of at least 80dB; measured at 2.5V input CM.Systematic input-referred offset < 250 µ V; measured at 2.5V input CM; assume perfectly matched devices (i.e., don’t worry about random offset).Follower rise and fall times (10-90%) < 250ns; measured with 0V to +3V step.Total on-chip resistance < 100k Ω ; assume the availability of perfect resistors, but only specify value to one significant digit (this applies also to the total value of a series or parallel string, so you can’t finesse your way out of this constraint that way).Device widths can be specified only in increments of 0.25 µ m.T = 25˚C; V DD = 5V; V SS =0V.Despite the fact that you are to meet these specifications at just one temperature and sup-ply voltage combination, your circuit must not be overly sensitive to either (i.e., no “mar-ble balanced on the tip of a cone” behavior). We will be the final judge of whether such a condition exists. If you are unsure, please consult the teaching staff early on.Use the SPICE level 3 models posted on the class website, NOT the level 1 models from the textbook (or any other place). That way, the only transcription errors will be ours.T. H. Lee Handout #14: EE214 Fall 2001 We require the following format for your report:Page 1: Schematic diagram, with component values and bias currents clearly indi-cated. Indicate component values right next to the components, and currents next to the branches (i.e., absolutely, positively do not make us refer to a look-up table; we will punish you if you do). The idea is to make it easy for us to figure out quickly what’s going on ( you try grading 100+ reports, and you’ll sympathize with this position!);Page 2: Summary table of specifications achieved, showing bandwidth as pre-dicted by open-circuit time constants, and summary of other specifications as predicted by hand calculations, all compared with what SPICE says;Page 3+: SPICE deck and output showing that your design meets all specifica-tions.The rest of the write-up must include a discussion of how you did the design, as well as a description of your final circuit. Please be succinct and clear; to enforce this requirement, this portion may not exceed 5 pages (not 5 sheets) of double-spaced text in 12 point Times font. Show your formulas (and values) for all specifications, including (but not limited to) gain and open-circuit time constants. Also comment on any discrepancies between your hand calculations (which should involve simplifying approximations that you clearly state) and SPICE (which uses everything). Be quantitative whenever possible . As a final note, leave all formulas in unexploded form, (e.g., if two resistors are in parallel, express that relationship as R 1 ||R 2 ).Be sure to check for announcements concerning this design problem. Questions concern-ing interpretation of specs, etc., invariably arise; we will post clarifications as needed. Fur-thermore, we will post instructions on how to submit your netlists electronically (we will use scripts to run HSPICE automatically so that everyone’s designs will be evaluated uni-formly and independently by us).While you are permitted, indeed encouraged, to discuss general design ideas with your classmates and staff, your design and write-up are to be individual efforts. Let your con-science and the spirit of the Honor Code guide you.Finally, and this is important: DON’T WAIT UNTIL THE LAST MINUTE TO START. This midterm involves a great deal of just plain old labor; it takes time to run all the neces-sary simulations for even one design, and most folks will go through several design itera-tions, especially since this midterm has an open-ended specification on gain. Also, the computers and printers in Sweet Hall and elsewhere have been known to slow down and even go down at the worst possible times. We will be largely unsympathetic to pleas for extensions arising from such problems. To encourage you to start early we make this offer: We will evaluate one of your preliminary designs with our (semi-)automated checker if you submit it electronically no later than 5pm, exactly one week before the final due date. That way, you can catch gross errors early enough to recover (or, more optimistically, discover that your answers agree with ours, and that you are done). Watch for instructions on how to submit your design. To keep out staff from overloading, we will insist on your slavish adherence to a standard submission format. If your submission does not run, it will simply not be