COMP 206: Computer Architecture and ImplementationOrganization of an InstructionClassification by OperandsInstruction Set Design Objective #1Instruction Set Design Objective #2Instruction Set Design Objective #3Instruction Set Design Objective #4Addressing ModesRegisters versus CacheOrganization of RegistersNotations for Information RepresentationWhy Is Numbering Important?Consequences of NumberingOdds and Ends about NumberingAlignment of Words in MemorySub-Word AccessesControl Transfer InstructionsCode Generation Examples for BranchesClassification of BranchesComputing Branch FrequenciesEvaluating Branch Conditions1COMP 206:COMP 206:Computer Architecture and Computer Architecture and ImplementationImplementationMontek SinghMontek SinghWed., Sep 8, 2004Wed., Sep 8, 2004Lecture 4: Lecture 4: Instruction Set DesignInstruction Set Design2U n i f o r mV a r i a b l eL e n g t hO p c o d eN u m b e rW h e r eH o w s p e c i f i e dO p e r a n d sS p e c i f i e r sF o r m a tS y n t a xP r o c e s s i n gD a t a m o v e m e n tT r a n s f e r o f c o n t r o lI / O o p e r a t i o n sS e m a n t i c sM a c h i n e i n s t r u c t i o nOrganization of an InstructionOrganization of an InstructionArithmeticLogicalShift(e.g., MIPS:4 bytes)(e.g., VAX:1-37 bytes)0 address1 address2 address3 addressimpliedInstructionRegisterMemoryAddressing modes•immediate•absolute•computedLoad (from MM)Store (to MM)Move (reg-reg)Move (MM-MM)Unconditional (branch)Conditional (jump)CallReturnIf I/O is notmemory-mapped1) Length of operands2) Shift/rotate: direction, amount3) Branch condition3Classification by OperandsClassification by OperandsStack Accumulator General Purpose RegisterLoa d/Store Reg/Mem Me m/MemALU operations 0 address 1 address 3 address 2 (or 1.5) address 3 addressExplicit operands (1,1) (0,3) (1,2), (1, 3), (2, 2) (3, 3)Instruction size Short Short 4 bytes 2/4/6 bytes variableNeeds separate Load/Store Load/Store Load/Store StoreEarly examples Burroughs PDP-8 CDC 6600 IBM S/360 DEC VAX-11/780B5000- Intel 8086 IBM S/370B7500 Motorola 6809Current examples Transputer All RISC machines IBM 3033, IBM S/390Amdahl VHitachi, FujitsuOrthogonality Farthest from Intermediate Closest toPipelining Easiest Intermediate HardestImportant machines that are difficult to classifyImportant machines that are difficult to classifyIntel 80x86Intel 80x86variable instruction size: 1-17 bytesvariable instruction size: 1-17 bytesmemory can be destinationmemory can be destinationuses implied registersuses implied registersMotorola 680x0Motorola 680x0Instruction size: 2, 4, 6, 8, 10 bytesInstruction size: 2, 4, 6, 8, 10 bytesTwo address format only (2, 2)Two address format only (2, 2)(m,n) means m memory operands n total operands(m,n) means m memory operands n total operands4Instruction Set Design Objective Instruction Set Design Objective #1#1Code size (code density) :Code size (code density) :Depends on:Depends on:size of MM/cachesize of MM/cacheaccess time of cache (on-chip/off-chip)access time of cache (on-chip/off-chip)CPU-MM bandwidthCPU-MM bandwidthFrequently used (written down) instructions should be Frequently used (written down) instructions should be shortshortImplies variable-length instructionsImplies variable-length instructions5Instruction Set Design Objective Instruction Set Design Objective #2#2Execution speed (performance) :Execution speed (performance) :Only frequently executed instructions should be Only frequently executed instructions should be included in the instruction setincluded in the instruction setInfrequently executed instructions slow down the othersInfrequently executed instructions slow down the othersComplex and long instructions tend to be used infrequentlyComplex and long instructions tend to be used infrequentlyDefining hardware-software interfaceDefining hardware-software interfaceFrequently executed instructions should be fastFrequently executed instructions should be fastPipelining should be made as easy as possiblePipelining should be made as easy as possibleOverlapped execution lowers CPI valueOverlapped execution lowers CPI valueSingle instruction length, simple instruction formats, and Single instruction length, simple instruction formats, and few addressing modes for easy decodingfew addressing modes for easy decodingThree (register) address instructions decouple CPU and Three (register) address instructions decouple CPU and memory, and also do not destroy their operands (reducing memory, and also do not destroy their operands (reducing memory accesses)memory accesses)6Instruction Set Design Objective Instruction Set Design Objective #3#3Size and complexity of hardware (ALU, CU) Size and complexity of hardware (ALU, CU) Implementing infrequently executed instructions ties Implementing infrequently executed instructions ties down hardware that is rarely used, and could be used down hardware that is rarely used, and could be used for some other purpose with greater advantagefor some other purpose with greater advantageSome instructions should not be included in the Some instructions should not be included in the instruction setinstruction set7Instruction Set Design Objective Instruction Set Design Objective #4#4Instruction set as a programming language Instruction set as a programming language Needs of a human programmer (less important today)Needs of a human programmer (less important today)Several desirable properties of instruction sets have been Several desirable properties of instruction sets have been recognized and described, such as orthogonality (each operand recognized and described, such as orthogonality (each operand can be specified independently of the others) and consistency can be specified independently of the others) and consistency (being able to predict the remainder of an architecture given (being able to predict the remainder of an architecture given partial knowledge of the system)partial knowledge of the system)Needs of an optimizing compilerNeeds of an optimizing compilerSimple instructions are more suitable for code optimizationsSimple instructions are more suitable for code optimizationsOptimizing compilers try to find the shortest or fastest code Optimizing compilers try to find the shortest or fastest code sequence that implements the semantics of a HLL program. To sequence that implements the semantics of a HLL program. To