1. (11) True or False:(1) DRAM and Disk access times are rapidly converging.(1) Measuring performance on multiprocessors using linear speedup instead of executiontime is a good idea.(1) Amdahl’slaw applies to parallel computers.(1) You can predict cache performance of Program A by analyzing Program B.(1) Computer components fail suddenly,with little warning.(1) Linear speedups are not needed to makemultiprocessors cost-effective.(1) It is not necessary to simulate very manyinstructions in order to get an accurate perfor-mance measure of the memory heirarchy.(1) A program’slocality behavior is constant overthe run of an entire program.(1) Communication is a significant problem for parallel processor systems.(1) Memory Bandwidth is the most important thing when designing a memory system.(1) The instruction set architecture impacts the implementability of a virtual machine moni-tor.2. (3) What is the goal of the memory heirarchy? What twoprinciples makeitwork?3. (9) What do the following acronyms stand for:OLTP VMM SRAMSMP TPC COMANUMA MPP DSM4. (4) What are the four classifications of cache misses?5. (1) Which type of cache miss can be changed by altering the mapping scheme?6. (1) Which type of cache miss can be reduced by using longer lines?7. (1) Which type of cache miss can be increased by using longer lines?Circle the correct answer:8. (1) Relaxing the requirement that Writes complete before Reads yields a model known asTotal Store Ordering Partial Store Ordering Weak Ordering9. (1) Relaxing the requirement that Writes complete before Writes yields a model known asTotal Store Ordering Partial Store Ordering Weak Ordering10. (1) Which type of operation is necessary in order to support synchronization?Nuclear Atomic Radioactive11. (1) Which benchmarks are most affected by the windowsize?Integer Float Equally affected12. (1) Which benchmarks are most affected by the accuracyofthe branch predictor?Integer Float Equally affected13. (1) Alias analysis has the most impact on which benchmark?Integer Float Equally affected14. (7) Which of the following does the book list as techniques for reducing the Miss Rate? (Cir-cle the correct answers)Small and simple caches Larger block sizeBigger caches WaypredictionTrace caches Higher associativityMultilevelcaches Pipelined cachesNon-blocking caches Multibanked cachesCompiler optimizations Victim cachePriority to Read Misses Critical Word First/Early RestartMerging Write Buffer Avoiding Address Translation when Indexing CacheHardware Prefetching Software prefetching15. (4) Which of the following does the book list as techniques for reducing the Hit Time? (Cir-cle the correct answers)Small and simple caches Larger block sizeBigger caches WaypredictionTrace caches Higher associativityMultilevelcaches Pipelined cachesNon-blocking caches Multibanked cachesCompiler optimizations Victim cachePriority to Read Misses Critical Word First/Early RestartMerging Write Buffer Avoiding Address Translation when Indexing CacheHardware Prefetching Software prefetching16. (7) Which of the following does the book list as techniques for reducing the Miss Penalty?(Circle the correct answers)Small and simple caches Larger block sizeBigger caches WaypredictionTrace caches Higher associativityMultilevelcaches Pipelined cachesNon-blocking caches Multibanked cachesCompiler optimizations Victim cachePriority to Read Misses Critical Word First/Early RestartMerging Write Buffer Avoiding Address Translation when Indexing CacheHardware Prefetching Software prefetchingShort Answers:17. (8) Describe the difference between shared memory and message passing machines.Include the impact on design, cost, and programming model.18. (8) What is Cache Coherence, and whyisitnecessary? Snooping is one main approach toproviding coherence - state what the other main approach is, and briefly outline howeach ofthem work.19. (6) What is an instruction window? Howdoes it impact ILP?20. (5) What pair of instructions are used to implement a lock in RISC systems (as described inthe text)? Describe howthis pair works together in order to accomplish the goal.21. (7) What is simultaneous multithreading? What characteristics of multi-issue processors isthis trying to takeadvantage of? (Be relatively detailed in your answer)22. (4) Assume a relatively large fully associative write-back cache that contains no valid data.Giventhe following sequence of 5 memory operations (the address of the operation is in thesquare brackets):WriteMem[100]ReadMem[100]WriteMem[100]WriteMem[200]WriteMem[100]What are the number of hits and misses when using write allocate versus no-write allocate?23. (4) Suppose you want to achieve a speedup of 80 with 100 processors. What fraction of theoriginal computation can be sequential? (Full credit if you showyour work, half-credit if youjust write the answer.)24. (4) Assume that L2 has a block size four times that of L1. Showhow a miss for an addressthat causes a replacement in L1 and L2 can lead to a violation of the inclusion