Hardware Implementation of Twofish Block CipherIntroductionGoals of this projectTwofish Encryption OverviewTwofish Pin-out DiagramFunction FPermutation StructureS-keys (S0,S1) GenerationRound Key GenerationKey SchedulingControl SignalsTools UsedFPGA Implementation Results(1)FPGA Implementation Results(2)ASIC Implementation ResultsProblems EncounteredConclusionHardware Implementation of Twofish Block CipherRanjeeta PatilIntroduction Twofish- one of the five finalists chosen for AES Commended by analyst for its security and flexibility 128-bit Block Cipher Supports key sizes of 128, 192 and 256 bitsGoals of this project Implementation of Twofish in hardware Key size of 128-bits Targeting both FPGAs and ASIC platforms FPGA Implementation- Xilinx SPARTAN 3 ASIC Implementation – 90 nm, 130 nm technologiesTwofish Encryption OverviewTwofish Pin-out DiagramKey InputKey AvailableKey Read128Data InputData AvailableData Read128Data Output128Data WriteFIFO FullClockResetEncr/DecrTwofish Block CipherK3P0+P3+P1+P2+ROL1ROL1ROR1ROR1+++++ +C0C1C2C3F functionK0K1K2K4K5K7K6S0S1K2r+8K2r+9eeeeddddE/DE/DE/DE/D00001111XORPseudo-Hadamard TransformK2r+8q0q1q0q1q0q0q1q1q0q1q0++S0S1ROL8Fin2Fin1MDS<<<1PHTK2r+9Fout1Function Fq1mod 232addition+S-boxesg- functionXx0x1x2x3y0y1y2y3ZZq0q1q0q1q0q0q1q1q0q1q0++MDSq1Xx0x1x2x3y0y1y2y3Fout2Permutation Structure+ROR1a0(0),0,0,0+t0t1+ROR1+t2t3a0b0a2b1a1b2a3b3b4a4xya0(0),0,0,0 a0,b0= x mod 16 a1= a0XOR b0b1= a0 XOR ROR(b0,1) XOR 8a0mod 16 a2, b2= t0[a1], t1[b1] a3= a2XOR b2b3= b2XOR ROR(b2,1) XOR 8 a2mod 16 a4, b4= t2[a3], t3[b3] y = 16 a4+ b4S-keys (S0,S1) GenerationReed Solomon matrixq0q1q0q1q0q0q1q1q0q1q0++MDSq1q0q1q0q1q0q0q1q1q0q1q0++MDSq1ROL8ROL9<<<1PHT2i2i2i2i2i+12i+12i+12i+1M2 M0M3M1K2r+8K2r+9Round Key GenerationKey GenerationReg0Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7K2r+8K2r+93232Up counter (0 to 3)Down counter (3 downto 0)Up-Down counter (4 to 19)8888K0K2K4K6K3K5K1K73232323232 32 32 32Key SchedulingK0,1K8,9K10,11K32,33K34,35K36,37K38,39K2,312K4,53K6,754KP8920 21 22 2367Control SignalsClkResetE/DKey_InputKey_availData_availData_ReadFIFO_fullData_WriteKey_ReadData_InputCData_OutputTools Used Design Entry Aldec Active HDL FPGA Implementation Synplicity Synplify Pro 8.0 Xilinx ISE 7.1 ASIC Synthesis Synopsys Design CompilerFPGA Implementation Results(1)Virtex family Device Used XCV-1000 No. of CLB slices: 1076 Max. Clk Freq: 22.1Mhz Throughput: 177 MbpsSpartan 3 family Device used: 3s200ft256 No. of 4-input LUTs: 3391 No. of CLB Slices: 1918FPGA Implementation Results(2)Timing Analysis Min. period= 44.33ns Max. Frequency= 22.55Mhz Throughput= 180.4MbpsThroughput =Block size No. of rounds X Min. Clk PeriodASIC Implementation Results Technology: 90 nm Area= 53753 sq. microns Min. period= 2.23 ns Max. Clock Frequency= 448 MHz Technology: 130 nm Area= 108664.15 sq. microns Min. period= 2.57 ns Max. Clock Frequency= 389 MHzProblems Encountered Problem with Endian-ness of inputs Multiplication over GF(28)Conclusion All specifications are met Results are comparable to previous implementation Throughput of the design can be improved by pipelining the
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