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UIUC GE 423 - Parallel Interfacing

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ClockCE2 EA[21:2] ED[31:0] ARE AWE …Figure 3: Timing Diagram for a Read CycleClockCE2 CE2 EA[21:2] ED[31:0] ARE ARE AWE AWE …Figure 3: Timing Diagram for a Read CycleCE2EA[21:2]ED[31:0]AREAWE…Figure 1: Timing Diagram for a Write CycleCE2CE2EA[21:2]ED[31:0]AREAREAWEAWE…Figure 1: Timing Diagram for a Write CycleParallel Interfacing Write Cycle Read CycleOMAP-L138www.ti.comSPRS586D– JUNE 2009– REVISED OCTOBER 2011Table 2-4. Top Level Memory Map (continued)Start Address End Address Size ARM Mem DSP Mem Map EDMA Mem PRUSS Mem Master LCDCMap Map Map Peripheral MemMem Map Map0x01F0 8000 0x01F0 8FFF 4K ECAP 20x01F0 9000 0x01F0 BFFF0x01F0 C000 0x01F0 CFFF 4K Timer20x01F0 D000 0x01F0 DFFF 4K Timer30x01F0 E000 0x01F0 EFFF 4K SPI10x01F0 F000 0x01F0 FFFF0x01F1 0000 0x01F1 0FFF 4K McBSP0 FIFO Data0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data0x01F1 2000 0x116F FFFF0x1170 0000 0x117F FFFF 1024K DSP L2 ROM(2)0x1180 0000 0x1183 FFFF 256K DSP L2 RAM0x1184 0000 0x11DF FFFF0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM0x11E0 8000 0x11EF FFFF0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM0x11F0 8000 0x3FFF FFFF0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0)0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2)0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3)0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4)0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5)0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs0x6800 8000 0x7FFF FFFF0x8000 0000 0x8001 FFFF 128K Shared RAM0x8002 0000 0xAFFF FFFF0xB000 0000 0xB000 7FFF 32K DDR2 Control Regs0xB000 8000 0xBFFF FFFF0xC000 0000 0xDFFF FFFF 512M DDR2 Data0xE000 0000 0xFFFC FFFF0xFFFD 0000 0xFFFD FFFF 64K ARM localROM0xFFFE 0000 0xFFFE DFFF0xFFFE E000 0xFFFE FFFF 8K ARM InterruptController0xFFFF 0000 0xFFFF 1FFF 8K ARM local ARM LocalRAM RAM (PRU0only)0xFFFF 2000 0xFFFF FFFF(2) The DSP L2 ROM is used for boot purposes and cannot be programmed with application codeCopyright © 2009–2011, Texas Instruments Incorporated Device Overview 25Submit Documentation FeedbackProduct Folder Link(s): OMAP-L138page1phone: 360.260.2468 l sales: 800.736.0194 l fax: 360.260.2469email: [email protected] l website: www.usdigital.com11100 ne 34th circle l vancouver, washington 98682 USALS7266R1Encoder to Microprocessor Interface ChipChipThe LS7266R1 is an LSI monolithic CMOS building block useful in motioncontrol applications. The two 24-bit multimode counters, registers, andlogic enables a microprocessor to track the speed, direction, position, andindex of one or two optical incremental encoders. In addition to an 8-bit databus, programmable real-time inputs and outputs are provided for hardwarebased control functions and status indication.Note:US Digital has already designed the IC's on this data sheet into variousproducts. Please see the PC7266, AD5 or ED2.Features:Ø X4 or X1 resolution multiplication.Ø Two preloadable 24-bit Up/Down counters.Ø Choice of two 20-pin packages: SOIC surface mount or DIP (600mil).Ø X1 or X2 or X4 resolution multiplier.Ø Binary, BCD, Divide-by-N, Range Limit, Non-Recycle & Non-quadrature Modes.Ø 2-axis 24-Bit comparators.Ø Independent mode programmability for each axis.Ø 17 MHz in quadrature mode.Ø 4 control registers.Ø Readable status flag register.Ø Digital filtering of the input quadrature clocks.Ø Programmable 8-bit separate filter clock prescalers for each axis.Ø Error flags for excess noise.Ø 8-Bit tri-state I/O bus.Ø Latched counter outputs.Ø Input/Output TTL & CMOS compatible.Ø 5 volt operation.Block Diagram of Counter & Registers: Ordering Information:Description:Technical Data, Rev. 11.21.00, November 2000All Information subject to change without notice.DIP Package (600mil):LS7266R1-DIPSurface Mount Package:LS7266R1-SOICPrice:$16.55 / 1$13.25 / 25$10.60 / 100$9.00 / 500$7.65 / 1KRDCSC/DX/YDBVALIDDATAVALID DATAtr1 tr10tr2tr3tr4tr5tr6tr7tr8tr9FIGURE 1. READ CYCLEtw5tw7tw9tw3tw2tw4tw6tw8INPUT DATAtw1 tw10INPUT DATAWRCSC/DX/YDBFIGURE 2. WRITE CYCLEt1 t2t3t5t4 t4 t4 t4t5FIGURE 3. FILTER CLOCK FCK AND QUADRATURE CLOCKS A AND BFCKFCKn(Note 4)ABNote 4: FCKn is the final modulo-n internal filter clock, arbitrarily shown here as modulo-1.DB_A21-18 DB_A2-5 DB_D0-7 DB ARE DB_AWE C6713 DSK 74F521AOBAddress Dip CS A0 A1 Pulled High D0-7 GATE2 CTS82C54 CS RD C/D A/B IN D0-7 LS7266R1 ENC. IN PWM1 DB_D0-7 DB_CE2 GATE0 GATE1 CLK0-2 OUT0 OUT2 OUT1 PWM2 10MHz DB_A3 DB_A2 DB_A3 DB_A2 DB_D0-7 DB_A4 DB_A5 Board Select DB_AWEDB AREDB AREDB_AWECS CS RD WR WR EN


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UIUC GE 423 - Parallel Interfacing

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