CSC 4320/6320 Operating Systems Lecture 8 Main MEMORYChapter 8: Memory ManagementObjectivesBackgroundBase and Limit RegistersHW Address Protection with Base & Limit RegistersBinding of Instructions and Data to MemoryMultistep Processing of a User ProgramLogical vs. Physical Address SpaceMemory-Management Unit (MMU)Dynamic relocation using a relocation registerDynamic LoadingDynamic LinkingSwappingSchematic View of SwappingContiguous AllocationHardware Support for Relocation and Limit RegistersContiguous Allocation (Cont)Dynamic Storage-Allocation ProblemFragmentationPagingAddress Translation SchemePaging HardwarePaging Model of Logical and Physical MemoryPaging ExampleFree FramesImplementation of Page TableAssociative MemoryPaging Hardware With TLBMemory ProtectionValid (v) or Invalid (i) Bit In A Page TableShared PagesShared Pages ExampleStructure of the Page TableHierarchical Page TablesTwo-Level Page-Table SchemeTwo-Level Paging ExampleAddress-Translation SchemeThree-level Paging SchemeHashed Page TablesHashed Page TableInverted Page TableInverted Page Table ArchitectureSegmentationUser’s View of a ProgramLogical View of SegmentationSegmentation ArchitectureSegmentation Architecture (Cont.)Segmentation HardwareExample of SegmentationExample: The Intel PentiumLogical to Physical Address Translation in PentiumIntel Pentium SegmentationPentium Paging ArchitectureLinear Address in LinuxThree-level Paging in LinuxEnd of Lecture 8Saurav KarmakarChapter 8: Memory ManagementBackgroundSwapping Contiguous Memory AllocationPagingStructure of the Page TableSegmentationExample: The Intel PentiumObjectivesTo provide a detailed description of various ways of organizing memory hardwareTo discuss various memory-management techniques, including paging and segmentationTo provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with pagingBackgroundProgram must be brought (from disk) into memory and placed within a process for it to be runMain memory and registers are only storage CPU can access directlyRegister access time is one(or less) CPU clockMain memory access can take many cyclesCache sits between main memory and CPU registersProtection of memory required to ensure correct operationBase and Limit RegistersA pair of base and limit registers define the logical address space of a processHW Address Protection with Base & Limit RegistersBinding of Instructions and Data to MemoryAddress binding of instructions and data to memory addresses can happen at three different stagesCompile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changesLoad time: Must generate relocatable code if memory location is not known at compile timeExecution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers)Multistep Processing of a User ProgramLogical vs. Physical Address SpaceThe concept of a logical address space that is bound to a separate physical address space is central to proper memory managementLogical address – generated by the CPU; also referred to as virtual addressPhysical address – address seen by the memory unitLogical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding schemeMemory-Management Unit (MMU)Hardware device that maps virtual to physical addressIn MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memoryThe user program deals with logical addresses; it never sees the real physical addressesDynamic relocation using a relocation registerDynamic LoadingRoutine is not loaded until it is calledBetter memory-space utilization; unused routine is never loadedUseful when large amounts of code are needed to handle infrequently occurring casesNo special support from the operating system is required implemented through program designDynamic LinkingLinking postponed until execution timeSmall piece of code, stub, used to locate the appropriate memory-resident library routineStub replaces itself with the address of the routine, and executes the routineThere are system also known as shared librariesOperating system needed to check if routine is in processes’ memory addressSwappingA process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued executionBacking store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory imagesRoll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executedMajor part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swappedModified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)System maintains a ready queue of ready-to-run processes which have memory images on diskSchematic View of SwappingContiguous AllocationMain memory usually divided into two partitions:Resident operating system, usually held in low memory with interrupt vectorUser processes then held in high memoryRelocation registers used to protect user processes from each other, and from changing operating-system code and dataBase register contains value of smallest physical addressLimit register contains range of logical addresses – each logical address must be less than the limit register MMU maps logical address dynamicallyHardware Support for Relocation and Limit RegistersContiguous Allocation (Cont)Multiple-partition allocationFixed-partition; Variable-partitionHole – block of available memory; holes of various size are scattered throughout memoryWhen a process arrives, it is allocated memory from a hole large enough to accommodate itOperating system maintains information about:a) allocated partitions b) free partitions (hole)OSprocess 5process 8process 2OSprocess 5process 2OSprocess 5process 2OSprocess 5process 9process 2process 9process 10Dynamic
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