Hardware Description Language 1 B RAMAMURTHY 01 14 19 HDL 2 Your goal in this class is to be able to design hardware organization of digital processors How do you specify this hardware design or model its components modules instances and interface ports to the external world Using a language that we can easily specify and understand VHDL is a older language Verilog is commonly used 01 14 19 HDL contd 3 As explained in your text The principal feature of a hardware description language is that it contains the capability to describe the function of a piece of hardware independently of the implementation The great advance with modern HDLs was the recognition that a single language could be used to describe the function of the design and also to describe the implementation This allows the entire design process to take place in a single language and thus a single representation of the design 01 14 19 Verilog 4 The Verilog Hardware Description Language usually just called Verilog was designed and first implemented by Phil Moorby at Gateway Design Automation in 1984 and 1985 Verilog simulators are available for most computers at a variety of prices and which have a variety of performance characteristics and features Verilog is more heavily used than ever and it is growing faster than any other hardware description language It has truly become the standard hardware description language 01 14 19 Verilog 5 A Verilog model is composed of modules A module is the basic unit of the model and it may be composed of instances of other modules A module which is composed of other module instances is called a parent module and the instances are called child modules comp1 comp2 system sub 3 01 14 19 Verilog Design Concept 6 System instantiates comp1 comp2 comp2 instantiates sub3 System comp 1 comp 2 sub3 01 14 19 Verilog Module Example 7 module shift shiftOut dataIn shiftCount parameter width 4 output width 1 0 shiftOut input width 1 0 dataIn input 31 0 shiftCount assign shiftOut dataIn shiftCount endmodule This module can now be used for shifters of various sizes simply by changing the width parameter Parameters can be changed per instance shift sh1 shiftedVal inVal 7 instantiation of shift module defparam sh1 width 16 parameter redefinition 01 14 19 Net component connectors 8 Nets are the things that connect model components together They are usually thought of as wires in a circuit Nets are declared in statements like this net type range delay3 list of net identifiers or net type drive strength range delay3 list of net decl assignments Example wire w1 w2 tri 31 0 bus32 wire wire number 5 wire number 2 wire number 3 here represents AND operation AND gate 01 14 19 Register 9 Registers are storage elements Values are stored in registers in procedural assignment statements Typical register declarations would be reg r1 r2 reg 31 0 bus32 integer i real fx1 fx2 Register can take 0 1 x unknown and z high impedence 01 14 19 Register Types 10 There are four types of registers 1 Reg This is the generic register data type A reg declaration can specify registers which are 1 bit wide to 1 million bits wide A register declared as a reg is always unsigned 2 Integer Integers are 32 bit signed values Arithmetic done on integers is 2 s complement 3 Time Registers declared with the time keyword are 64 bit unsigned integers 4 Real and Realtime Real registers are 64 bit IEEE floating point Not all operators can be used with real operands Real and realtime are synonymous 01 14 19 Primitives 11 Primitives are pre defined module types They can be instantiated just like any other module type The Verilog primitives are sometimes called gates because for the most part they are simple logical primitives 1 output and nand or nor 1 input buf not Etc 01 14 19 Example 12 Primitives are instantiated in a module like any other module instance For example the module represented by this diagram would be instantiated module test ain n2 n1 wire n1 n2 bin reg ain bin and and prim n1 ain bin not not prim n2 n1 endmodule 01 14 19 Assign 13 Continuous assignments are sometimes known as data flow statements because they describe how data moves from one place either a net or register to another They are usually thought of as representing combinational logic Example assign w1 w2 w3 01 14 19 Lets get the Verilog module for this circuit 14 http www doulos com knowhow verilog de signers guide wire assignments 01 14 19 Solutions using assign and wire 15 module AOI input A B C D output F start of a block comment wire F wire AB CD O assign AB A B assign CD C D assign O AB CD assign F O end of a block comment Equivalent wire AB A B wire CD C D wire O AB CD wire F O endmodule end of Verilog code 01 14 19