FIFO Chip Design ExampleFIFO ExampleGetting StartedMOSIS Pad framePackaged PartSample Pad frameBonding DiagramHow big a FIFO can we make?Saving SpaceTrade offsSlide 11Slide 124 DFF’sDerivative DFF DesignNot D Internal Routing UpDFF_DI_RUDFF_DI_RDDFF_DE_RUSlide 19DFF_DE_RDDFF_INVDesign ReviewNew DFF StructureBack to the FIFOGut check on power30 MHz! What happened to 200MHz?FIFO SchematicSlide 28FIFO Schematic CompleteFIFO SymbolPowerPoint PresentationVerilog Test benchSlide 33Input VectorsSlide 35Slide 36OutputSlide 38Spice SummaryLayoutLayout with only cellsRoute VDD and GroundFinal FIFO LayoutFinal Layout VerificationPost Extraction SimulationModify a Pad frameSample PadframeChange Pin 21 from padinc to padgndMake sure pads abut.Change pins 22-24 to unusedFIFO_PFCreate Pin NamesPin to Pin Test BenchFIFO_PF LayoutPAD I/OPAD VDD/GNDConnect a metal 2 path 2.7u wide to DIBDRCDo not DRC LayerFIF0_PF SymbolSlide 61Simulation TroubleSolutionsSlide 64Slide 65AnalysisOutputs Y15-Y8Outputs Y7-Y0Inputs A15-A8Inputs A7-A0Slide 71Statistics (Working alone in the middle of the summer)Design StatisticsDRC and Extract time vs. gate countSimulation time vs. gate countDesign time vs. gate countHow fast do I work?Slide 78Lessons LearnedEE166 FIFO Example 1FIFO Chip Design ExampleEE166SJSUDavid ParentEE166 FIFO Example 2FIFO Example•We will now try to put together the concepts of:–Cell based design–Super Buffer–Clock trees–IP reuse–Getting a chip into a Pad frame•FIFO–Simple, RegularEE166 FIFO Example 3Getting Started•The first thing we must do is decide the pins in an actual pad frame with the package.•This will give us the context we need to make intelligent decisions about routing.EE166 FIFO Example 4MOSIS Pad frame•The stand tiny chip from MOSIS can support 40 pins.•You need to start with the pin out of the actual packaged chip to make the part useable and testable.•We will use pin 1 as VDD and 21 as GND as a standard. This inputs will come in the top (2-20) and out puts in general will be out the bottom (21-40)•We will choose pin 2 for CK, 3 for NPRE and 4 for NCLR•A0-A15 will map to pins 5-20.•Y0-Y15 will map to pins 40-25.EE166 FIFO Example 5Packaged Part12345678910111213141516171819203130292827262524232221403938373635343332 DP40Pin# Pin Name Pin# Pin Name 1 VDD 40 Y0 2 CK 39 Y1 3 NPRE 38 Y2 4 NCLR 37 Y3 5 A0 36 Y4 6 A1 35 Y5 7 A2 34 Y6 8 A3 33 Y7 9 A4 32 Y8 10 A5 31 Y9 11 A6 30 Y10 12 A7 29 Y11 13 A8 28 Y12 14 A9 27 Y13 15 A10 26 Y14 16 A11 25 Y15 17 A12 24 UNUSED 18 A13 23 UNUSED 19 A14 22 UNUSED 20 A15 21 GND Note: I will not fab a part without the pins list!EE166 FIFO Example 6Sample Pad frameArea inside is 895m by 895m.You can get more area buy using less pins. (Read Data in serially?)You can have larger circuits but they use up more “MOSIS money”pin 1pin 21EE166 FIFO Example 7Bonding DiagramThis goesin the package.EE166 FIFO Example 8How big a FIFO can we make?•Our DFF is 72m x 36 m in area•A MOSIS tiny chip gives you about 900m x 900m of space Assume that we can only use ½ the space.–This can be increased if you use less than 40 pads.–Number of rows 450/36 gives 12–Number of columns 900/72 gives 12EE166 FIFO Example 9Saving SpaceWe could overlay the ground wires and save 3 m.We could overlay the clock and reset signals and save 10m.We could get rid of not clock by adding an inverterand save 3m.EE166 FIFO Example 10Trade offs•Replacing not clock with an inverter.–New Cell Height 33 (450/33 gives 13)–New Cell Width 72+8 (900/ gives 11)–Routing is easier–Do not have to worry about skew between not clock and clock–Will the power go up?•Maybe. You would need another super buffer to drive not clock. In this case you only need one.EE166 FIFO Example 11Trade offs•Overlay the reset and clock signals–New average Cell Height 31 (450/31 gives 14)–No New Cell Width –Need two DFF parts one flipped with different wiring to the global signals one unchanged•We already need two type of FF one with D and not D and the other with D input only. This would make 4 different FF!EE166 FIFO Example 12Trade offs•Overlay the ground signals–New average Cell Height 34.5 (450/34.5 gives 13)–No New Cell Width –Electro migration?•Nothing works!–We have to try it all!–Still only 15 wide!–We could shrink height by 3m which would give us 16 bits wide but then AOI logic would not fit into the cell height.–We beg the senior engineer for 50m more space.EE166 FIFO Example 134 DFF’s•All The FFs need to have the Not clock removed!•Need to have to verify 4 new parts from one old part!•This will take some time!•No choice.•New Average Cell Height 31.375 16 bits high will give less than 500 microns so it it will fit in the expanded space.40 min20 min Routing UP Routing Down Not D Internal DFF_DI_RU DFF_DI_RD Not D External DFF_DE_RU DFF_DE_RD 7 min5 minEE166 FIFO Example 14Derivative DFF DesignTime0510152025303540450 1 2 3 4 5DFF DesignTime (Mins.)TimeI really saved some time by reusing the same template.It also helped that my NAND3 was designed to have flexible routing, rather than minimum area.EE166 FIFO Example 15Not D Internal Routing Up•Not CK are provided by inverters to be added as required. Not D is generated by the NAND2 from D. Since we will not be operating at less than 1ns the increase setup time will not matter.EE166 FIFO Example 16DFF_DI_RUCKNCLRNPREDQ QNUse the nand as an inverter.EE166 FIFO Example 17DFF_DI_RDCK NPRE NCLREE166 FIFO Example 18DFF_DE_RUEE166 FIFO Example 19DFF_DE_RUD NDEE166 FIFO Example 20DFF_DE_RDD NDQ QNEE166 FIFO Example 21DFF_INVEE166 FIFO Example 22Design Review•After looking at the parts so far it looks like there could be an electro migration problem where the VDD is bought into the circuitSince all the FF use the same basic parts,We just have to fix it once in each cell.You can even edit it in place!I had to flatten the NTAP to do this.I had to add some nwell due to a DRC error.EE166 FIFO Example 23New DFF StructureEE166 FIFO Example 24Back to the FIFO•We can fit 16 bits high within 500 microns•We can fit 900/80 long (11)•We can do a FIFO 10 bits deep.•We will use 16 x 10 DFF (160)–8 DFF_DI_RU–8 DFF_DI_RD–72 DFF_DE_RU–72 DFF_DE_RDEE166 FIFO Example 25Gut check on power•160 DFF–Each one has 21 NMOS and 21 PMOS•This is like having 21 inverters•Total