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SJSU EE 166 - TESTING 4-BIT-ADDER

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TESTING 4-BIT-ADDER BY COUNTER AND WALKING ONESSPECIFICATIONS4-BIT-ADDER1-BIT ADDER SCHE.1-BIT ADDER LAYOUT1-BIT ADDER EXTRACTED VIEW1-BIT ADDER LVS1-BIT-ADDER-TRANSIENT RESPONSE1-BIT ADDER VERILOG1-BIT ADDER TEST BENCH4-BIT ADDER TEST BENCH4-BIT ADDER LAYOUT4-BIT ADDER EXTRACTED VIEW4-BIT ADDER LVS4-BIT ADDER TRANSIENT RESPONSE4-BIT ADDER VERILOGNAND3 SCHEMATICNAND3 LAYOUTNAND3 EXTRACTED VIEWNAND3 LVSNAND3 TRANSIENT RESPONSENAND3 TEST BENCHPowerPoint Presentation1 BIT D FLIP FLOP SCHEMATIC1 BIT D FLIP FLOP LAYOUT1 BIT D FLIP FLOP EXTRACTED VIEW1 BIT D FLIP FLOP LVS1 BIT D FLIP TRANSIENT RESPONSE1 BIT D FLIP TEST BENCH4-BIT BINARY COUNTERCOUNTER SCHEMATICCOUNTER LAYOUTCOUNTER EXTRACTED VIEWCOUNTER LVSCOUNTER TRANSIENT RESPONSECOUNTER TEST BENCHCOUNTER ADDER SCHEMATICCOUNTER ADDER LAYOUTCOUNTER ADDER EXTRACTED VIEWCOUNTER ADDER LVSCOUNTER ADDER TRANSIENT RESPONSECOUNTER ADDER TEST BENCH4 BIT SHIFT REGISTER SCHEMATIC4 BIT SHIFT REGISTER LAYOUT4 BIT SHIFT REGISTER EXTRACTED VIEW4 BIT SHIFT REGISTER LVS4 BIT SHIFT REGISTER TRANSIENT RESPONSE4 BIT SHIFT REGISTER TEST BENCH4 BIT SHIFT REGISTER ADDER SCHEMATIC4 BIT SHIFT REGISTER ADDER LAYOUT4 BIT SHIFT REGISTER ADDER EXTRACTED VIEW4 BIT SHIFT REGISTER ADDER LVS4 BIT SHIFT REGISTER ADDER TRANSIENT RESPONSE4 BIT SHIFT REGISTER ADDER TEST BENCH4 BIT SHIFT REGISTER ADDER POWERSlide 56TESTING 4-BIT-ADDER BY COUNTER AND WALKING ONESGROUP MEMBERS: DIEU-NHI LE (4-Bit-Adder) STEPHEN LAM (Shift Register) BAO DOAN (Counter) CHAU HOANG (Counter)SPECIFICATIONS•Timing:•Speed:•Power:Shift Register Adder: P=20.1mWCounter Adder: P=20.5mW•Total area:Shift Register Adder: A=0.13um^2Counter Adder: A=0.076um^24-BIT-ADDER- Testing 1-Bit, layout. -Testing 4-Bit, layout.-Verify the logic using Verilog.1-BIT ADDER SCHE.1-BIT ADDER LAYOUT1-BIT ADDER EXTRACTED VIEW1-BIT ADDER LVS1-BIT-ADDER-TRANSIENT RESPONSE1-BIT ADDER VERILOG1-BIT ADDER TEST BENCH4-BIT ADDER TEST BENCH4-BIT ADDER LAYOUT4-BIT ADDER EXTRACTED VIEW4-BIT ADDER LVS4-BIT ADDER TRANSIENT RESPONSE4-BIT ADDER VERILOGNAND3 SCHEMATICNAND3 LAYOUTNAND3 EXTRACTED VIEWNAND3 LVSNAND3 TRANSIENT RESPONSENAND3 TEST BENCHTRUTH TABLE FOR 7474 D FLIP-PLOPMode Inputs Outputsof Asynchr onous Synchronousoperation Set CLR CLK D Q QNAsynchronous set 0 1 X X 1 0Asynchronous reset 1 0 X X 0 1Prohibited 0 0 X X 1 1Set 1 1 1 1 0Reset 1 1 0 0 10 = low1 = highX = irrelevant↑ = low – to – high transition of the clock pulse1 BIT D FLIP FLOP SCHEMATIC1 BIT D FLIP FLOP LAYOUT1 BIT D FLIP FLOP EXTRACTED VIEW1 BIT D FLIP FLOP LVS1 BIT D FLIP TRANSIENT RESPONSE1 BIT D FLIP TEST BENCH4-BIT BINARY COUNTER•A four bit binary counter we have designed in this project counts down and with every clock input moves up to the next higher state. It was designed using D type flip-flops. It has a SET signal which is setting when it is equal to 1.A CLEAR signal sets the counter back to 0.1100110100111000100110100100011001010111001010110001000011101111COUNTER SCHEMATICCOUNTER LAYOUTCOUNTER EXTRACTED VIEWCOUNTER LVSCOUNTER TRANSIENT RESPONSECOUNTER TEST BENCHCOUNTER ADDER SCHEMATICCOUNTER ADDER LAYOUTCOUNTER ADDER EXTRACTED VIEWCOUNTER ADDER LVSCOUNTER ADDER TRANSIENT RESPONSECOUNTER ADDER TEST BENCH4 BIT SHIFT REGISTER SCHEMATIC4 BIT SHIFT REGISTER LAYOUT4 BIT SHIFT REGISTER EXTRACTED VIEW4 BIT SHIFT REGISTER LVS4 BIT SHIFT REGISTER TRANSIENT RESPONSE4 BIT SHIFT REGISTER TEST BENCH4 BIT SHIFT REGISTER ADDER SCHEMATIC4 BIT SHIFT REGISTER ADDER LAYOUT4 BIT SHIFT REGISTER ADDER EXTRACTED VIEW4 BIT SHIFT REGISTER ADDER LVS4 BIT SHIFT REGISTER ADDER TRANSIENT RESPONSE4 BIT SHIFT REGISTER ADDER TEST BENCH4 BIT SHIFT REGISTER ADDER POWER4 BIT SHIFT REGISTER ADDER


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