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SJSU EE 166 - Design of 8- Bit ALU

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Design of 8- Bit ALUAgendaAbstractKogge Stone Adder.Block DiagramIntroductionSchematicLongest Path CalculationsLogic Verification SumLogic Verification (contd.) XORLayoutLayout verificationTest BenchSimulationsCost AnalysisLessons LearntSummaryAcknowledgements1Design of 8- Bit ALUNeelam ChaudhariArchana MulukutlaNamita MittalMadhumita SanyalAdvisor : Dr. David ParentDate : May 8, 20062Agenda•Abstract•Introduction–Why–Theory behind.–Back Ground information (Lit. Review)•Summary of Results•Project (Experimental) Details•Results•Cost Analysis•Conclusions3AbstractWe designed 8- bit ALU using Kogge StoneTree Adder. Specifications:• Frequency : 200MHz• Area: 631 * 850 Sq.um• Power : 0.2mW Functionality:• Logical operations : A AND B, A XOR B• Arithmetic Operations : A+B4Kogge Stone Adder.1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:143:04:15:26:37:48:59:610:711:812:913:1014:1115:124:05:06:07:08:19:210:311:412:513:614:715:82:0012345678910111213141515:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0(retrieved from http://odin.ac.hmc.edu/~harris/class/e158/lect11.ppt#284,36,Kogge-Stone)5Block DiagramAOI 3333Propagate & Generate BlockCARRY NETWORKSUM GENERATORAOI 3333 :1 MUXOutputPG6IntroductionWhy this Project? •ALU is Basic Building Block of several circuits.•Challenging to implement CLA with least number of logic levels and fan-ins.•Look ahead across the look-ahead carry tree.•Gives us a hands-on design experience on the concepts learnt in EE166.7SchematicLongest Path8Longest Path CalculationsNote: All widths are in microns and capacitances in fFPropagation delay/ Logic level : 5ns/169Logic VerificationSumArithmetic Operation (A+B) A 10101111+B +10000101 00110100Cout110Logic Verification (contd.)XOR•Logical Function: A XOR BA 10101001B 10000000 0010100111LayoutDRC Verified12Layout verification13Test Bench14Simulations15Cost Analysis•Time spent on each phase of the project–Verifying logic - 3 Weeks–Verifying timing - 2 Weeks–Layout - 4 Weeks–Post Extracted Timing - 2 days16Lessons Learnt•Planning is very important.•Start early and have clear estimation of the work to be done.•Give more time for the layout stage.17Summary•Designed and tested almost all the design units learnt in the class.•This design can be modified to be used in higher order bit ALU’s and more functions. •We designed 8-Bit ALU working at 200 MHz speed ,driving 20fF load.18Acknowledgements•Thanks to Cadence Design Systems for the VLSI lab and Remote Login.•Thanks to Hummingbird for remote login.•Thanks to Professor David Parent for his valuable


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SJSU EE 166 - Design of 8- Bit ALU

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