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ISIT10_LDPCCodes



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ISIT 2010 Austin Texas U S A June 13 18 2010 LDPC Codes for Rank Modulation in Flash Memories Fan Zhang Electrical and Computer Eng Dept Texas A M University College Station TX 77843 fanzhang tamu edu Henry D P ster Anxiao Andrew Jiang Electrical and Computer Eng Dept Texas A M University College Station TX 77843 hp ster tamu edu Computer Science and Eng Dept Texas A M University College Station TX 77843 ajiang cse tamu edu Abstract An LDPC code is proposed for ash memories based on rank modulation In contrast to previous approaches this enables the use of long ECCs with xed length modulation codes For ECC design the rank modulation scheme is treated as part of an equivalent channel A probabilistic model of the equivalent channel is derived and a simple high SNR approximation is given LDPC codes over integer rings and nite elds are designed for the approximate channel and a low complexity symbol ipping veri cation based SFVB message passing decoding algorithm is proposed to take advantage of the channel structure Density evolution DE is used to calculate decoding thresholds and simulations are used to compare the low complexity decoder with sum product decoding I I NTRODUCTION Flash memories have become the most widely used nonvolatile memories NVMs due to their high performance They use the charge stored in oating gate cells to represent data Charge e g electrons can be injected into a cell by the hot electron injection mechanism or the Fowler Nordheim tunneling mechanism and be removed from the cell by the tunneling mechanism The amount of charge in a cell is called its level and we can quantize it into one of q values to store log2 q bits When q 2 it is called a single level cell SLC and when q 2 it is called a multi level cell MLC To increase data density MLC ash memories with more levels e g q 4 8 are being actively developed Flash memories have a distinct property called block erasure The ash memory cells are organized as blocks where every block consists of



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