Asynchronous Circuit DesignFundamental Mode Asynchronous CircuitAsynchronous Sequential CircuitExample 1- Logic DiagramExample 1- Excitation/Transition Table Y1 = x2’y1 +x1’y1+x1’x2y2 Y2 = x1y1+x2y1y2+x1y2+x1x2 z = x2’y1 +x1’y1y2+x1x2‘y2The State TableThe Flow TableThe Flow DiagramAsynchronous Sequential Network - SYNTHESISSynthesis of Asynchronous Sequential CircuitA. Partially completed Primitive Flow TableB. Primitive Flow TableC. Reduced Flow TableC. Reduced Flow Table Cont.D. Race Free AssignmentE. Excitation and Output TablesE. Excitation and Output Tables Cont.F. CircuitRace & Critical RaceRace – ExampleRace – Example Cont.AvoidanceAvoidance Cont.Slide 24Slide 25Race-Free State AssignmentMethod One (adding cycles)Method One Cont.Method Two: Universal state assignmentMethod Two Cont.Slide 31Slide 32EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisAsynchronous Circuit DesignIntroductionAnalysisSynthesisRacesStatic and dynamic hazardsEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisFundamental Mode Asynchronous CircuitCombDelayInputOutputExcitationStateSecondaryStateSingle Input ChangeAsynchronous Sequential CircuitAnalysisEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisExample 1- Logic DiagramEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisExample 1- Excitation/Transition TableY1 = x2’y1 +x1’y1+x1’x2y2Y2 = x1y1+x2y1y2+x1y2+x1x2z = x2’y1 +x1’y1y2+x1x2‘y20000101011111001100000010101101100000101110110 11ExcitationY1 Y2PSy1 y2Input State x1x2000110 110 0 0 00 0 1 01 0 1 01 1 1 0Output zInput State x1x2EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisThe State Table A A C C D D10BC0000B B01 C11 A A B BD0110 11Next StatePSInput State x1x2000110 110 0 0 00 0 1 01 0 1 01 1 1 0Output zInput State x1x200  A01  B10  C11  DEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisThe Flow Table A A C C D D10BC0000B B01 C11 A A B BD0110 11Next StatePSInput State x1x2000110 110 -- 0 ---- -- 1 01 0 -- ---- 1 1 --Output zInput State x1x2EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisThe Flow DiagramCDBAAsynchronous Sequential Network - SYNTHESISSynthesisRaces, Cycles, and HazardsEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisSynthesis of Asynchronous Sequential CircuitWhen x1x2=00, then z1z2=00Sequence x1x2=00 01 11, then z1z2=10. Output remains at 10 until x1x2=00, then z1z2=00Sequence x1x2=00 10 11, then z1z2=01. Output remains at 01 until x1x2=00, then z1z2=002 2x1x2z1z2EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisA. Partially completed Primitive Flow Tablex1x200 01 11 101 1 /00 -/-2 2 /00 -/-3 3 /10 -/-4 4 /01 -/-5 -/- 5 /106 -/- 6 /017 -/- 7 /008 -/- 8 /109 -/- 9 /01Before output changes from 00After output changes from 00Two successfulsequencesEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisB. Primitive Flow Tablex1x200 01 11 101 1 /00 2/00 -/dd 7/002 1/00 2 /00 5/d0 -/dd3 1/d0 3 /10 5/10 -/dd4 1/0d 4 /01 6/01 -/dd5 -/dd 3/10 5 /10 8/106 -/dd 4/01 6 /01 9/017 1/00 -/dd 6/0d 7 /008 1/d0 -/dd 5/10 8 /109 1/0d -/dd 6/01 9 /01Changes from 1 to 0Changes from0 to 1No change on outputEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisC. Reduced Flow Table23456789 1 2 3 4 5 6 7 8   56 )9,6,4(),8,5,3(),7,1(),2,1( a c b d123456789EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisC. Reduced Flow Table Cont.00 01 11 10a a /00 a /00 b/d0 c/00b a/d0 b /10 b /10 b /10c c /00 a/00 d/0d c /00d c /0d d /01 d /01 d /01EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisD. Race Free Assignmenta = 00b = 01c = 10d = 11a bdc11, 00011000,11a 00abb 01cac10d=11EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisE. Excitation and Output Tablesx1x2x1x200 01 11 10 00 01 11 1000 00 00 01 10 00 00 d0 00y1y201 00 01 01 01 d0 10 10 1010 10 00 11 10 00 00 0d 0011 10 11 11 11 0d 01 01 01y1y2z1z2EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisE. Excitation and Output Tables Cont.21221122212122211211211yyzyyzyxyxxxYxyxyxyxyyYEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisF. CircuitDeltaDeltaz1z2x1x2y1y2EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisRace & Critical RaceRace Definition: Two or more secondary state (yi) variables change during a transition between stable state. Depending on which variables change firstly, we may end up in an incorrect stable state (critical race). However, if the circuit ends up in a correct state irrespect of which variable changes firstly, we have a case of non-critical race.EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisRace – Examplex1x2x1x200 01 11 10 00 01 11 1000 00 01 00 01 0 0 1 1y1y201 00 01 10 01 0 0 0 010 00 10 10 11 1 1 0 011 00 10 00 11 0 0 1 1y1y2zEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisRace – Example Cont. x1 x2 y1 y2<1 0 1 1><0000>δ 1> δ 2 => 1011 => 0011 => 0010 => 0000δ 2> δ 1 => 1011 => 0011 => 0001 => 0000δ 1> δ 2 => 1001 => 1101 => 1100 => 1100We want to go from 01 to 10, but this change first before y1 change from 0 to 1δ 2> δ 1 => 1001 => 1101 => 1111 => 1110Non CriticalNot CorrectCorrectEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisAvoidance00 01 11 10a a/0 b/0 a/1 b/1b a/0 b/0 c/0 b/0c a/1 c/1 c/0 d/0d a/0 c/0 a/1 d/1Critical RaceCol 01 => b, cCol 11 => a, cCol 10 => d, bEE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisAvoidance Cont.a bd c0110001100110010a bd c0110111110EE270 Asynchronous Sequential Network - SYNTHESIS Dr. Tri Caohuu © 2006 Andy DavisAvoidance Cont.Let a = 00 ab => b = 01bc = 01 => c = 11 cd => d = 10EE270 Asynchronous Sequential Network -