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UCD ECS 201A - Study Notes

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1. (12) True or False:(1) DRAM and Disk access times are rapidly converging.(1) Measuring performance on multiprocessors using linear speedup instead of executiontime is a bad idea.(1) Computer systems achieve 99.999% availability ("fivenines"), as advertised.(1) Computer components fail suddenly,with little warning.(1) Amdahl’slaw applies to parallel computers.(1) You can predict cache performance of Program A by analyzing Program B.(1) Linear speedups are needed to makemultiprocessors cost-effective.(1) Scalability is almost free.(1) A program’slocality behavior is constant overthe run of an entire program.(1) Operating systems are the best place to schedule disk accesses.(1) Communication is not a significant problem for parallel processor systems.(1) The instruction set architecture does not impact the implementability of a virtualmachine monitor.2. (3) What is the goal of the memory heirarchy? What twoprinciples makeitwork?3. (15) What do the following acronyms stand for:SMT SMP MTTFCOMA RAID RAWNUMA MPP DSMMTTR SRAM ILPVMM OLTP TPC4. (1) Which benchmarks are most affected by the windowsize? (Circle the correct answer)integer float equally affected5. (1) Which benchmarks are most affected by the accuracyofthe branch predictor? (Circle thecorrect answer)integer float equally affected6. (1) Alias analysis has the most impact on which benchmark? (Circle the correct answer)integer float equally affected7. (7) Which of the following does the book list as advanced optimizations of cache perfor-mance? (Circle the correct answer)Small and simple caches Larger block sizeBigger caches WaypredictionTrace caches Higher associativityMultilevelcaches Pipelined cachesNon-blocking caches Multibanked cachesCompiler optimizations Victim cacheShort Answers:8. (3) What is a victim cache, and howdoes it work?9. (4) Cache misses can be catagorized into 4 different types. What are the four types of cachemisses?10. (6) What is an instruction window? Howdoes it impact ILP?11. (7) What is simultaneous multithreading? What characteristics of multi-issue processors isthis trying to takeadvantage of? (Be relatively detailed in your answer)12. (8) What is Cache Coherence, and whyisitnecessary? Snooping is one main approach toproviding coherence - state what the other main approach is, and briefly outline howeach ofthem work.13. (8) What type of operation is required to support synchronization? (Hint - the answer I’mlooking for starts with an "A"). What pair of instructions are used to implement a lock in RISCsystems (as described in the text)? Describe howthis pair works together in order to accomplishthe goal.14. (8) Assume a relatively large fully associative write-back cache that contains no valid data.Giventhe following sequence of 5 memory operations (the address of the operation is in thesquare brackets):WriteMem[100]WriteMem[100]ReadMem[200]WriteMem[200]WriteMem[100]What are the number of hits and misses when using write allocate versus no-write allocate?15. (8) Suppose you want to achieve a speedup of 80 with 100 processors. What fraction of theoriginal computation can be sequential? (Full credit if you showyour work, half-credit if youjust write the answer.)16. (8) Assume that words A and B are in twodifferent locations in the same cache block, whichis in the shared state in the caches of both P1 and P2. In the following sequence of events, iden-tify each miss as either a true sharing miss, a false miss, a sharing miss, or a hit. (Anymiss thatwould occur if the block size were one word is referred to as a true sharing miss.)Time P1 P21Write A2Read B3Write A4Write B5Read BForexample, the event at time 1 is a true sharing miss, because A was read by P2 and needs to beinvalidated from P2. Foreach event 2-5, list what type of miss


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UCD ECS 201A - Study Notes

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