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Bucknell ELEC 350 - MOSFET Amplifier Bias Design

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Lab #11: MOSFET Amplifier Bias DesignIntroductionExperimental ProcedureELEC 350L Electronics I Laboratory Fall 2011Lab #11: MOSFET Amplifier Bias DesignIntroductionBiasing is the process of selecting component values in an amplifier so that the proper quiescent voltages and currents in the circuit are established to meet a set of design goals. A frequent requirement is to have the quiescent voltages and currents remain close to target values in spite of variations in device parameters. In other situations the repeatability of specific voltage and current levels is not so important, but their stability in spite of temperature changes or other environmental variations is important. In this lab exercise you will design and test a bias circuit for a 2N7000 n-channel enhancement-mode MOSFET.Theoretical BackgroundBias levels in MOSFET amplifiers are often stabilized using the source degeneration technique, in which a resistor is placed between the device’s source and ground. The resistor introduces negative feedback that forces the quiescent drain current to remain close to its design value regardless of changes in the MOSFET’s parameters (kn or kp, and Vt) or environmental conditions. Shown in Figure 1 is a common-source MOSFET amplifier that uses this bias stabilization method. If the drain current ID begins to rise above its intended quiescent value, the voltage drop across RS increases. Since the gate-source voltage VGS is the difference between the gate potential VG and the voltage across RS, a rise in the voltage across RS causes VGS to drop, which in turn causes ID to move back toward its original value. Gate voltage VG is usually very stable because it is established by the voltage divider formed by RA and RB. The opposite chain ofevents occurs if ID begins to drop below its intended value.Figure 1. Common-source amplifier using an n-channel enhancement-mode MOSFET with source degeneration. The capacitors, source vg, and load RL are connected by dashed lines to indicate that they do not affect the DC biasing of the circuit.VDD RARBRDVDVGIDRSvgCi+−CoRLVGS−+VS+VDS−1 of 6The quiescent drain current ID in an amplifier with source degeneration must simultaneously satisfy the two relations 221tGSnDVVkI  and SDGGSRIVV ,where Vt is the threshold voltage of the MOSFET, and kn is its transconductance parameter, givenbyLWCkoxnn,where n is the mobility of the free electrons in the inversion channel, Cox is the capacitance per unit area between the gate and the inversion channel, and W and L are the width and length, respectively, of the channel. The quantity VG is the gate voltage measured with respect to ground.Combining the two ID-VGS equations by eliminating VGS leads to a quadratic equation:    222121SDtGntSDGnDRIVVkVRIVkI     222221SDSDtGtGnDRIRIVVVVkI    22222SDSDtGtGnDRIRIVVVVkI   022222tGDntGSDSVVIkVVRIR.The solution is            tGSnSnSnStGtGSnnSSnStGntGnSSSnStGtGSntGnStGSSSnStGtGSntGSSSnStGDVVRkRkRkRVVVVRkkRRkRVVkVVkRRRkRVVVVRkVVkRVVRRRkRVVVVRkVVRRRkRVVI211112421148211448421142221122222222222222222222.The sign ambiguity is resolved by applying the constraint VGS > Vt. Since VGS = VG – IDRS, thenDStGtSDGtGSIRVVVRIVVV .Substituting the expression for ID into the inequality makes it evident that the lower sign (− in theexpression above) corresponds to the physically meaningful solution:2 of 6  tGSnSnSntGSnSnSnStGStGDStGVVRkRkRkVVRkRkRkRVVRVVIRVV2111021112222 correct) issign (lower 211122tGSnSnSnVVRkRkRk Thus, tGSnSnSnStGDVVRkRkRkRVVI  211122.A plot of this expression for ID versus kn shows that the drain current is relatively insensitive to this parameter. However, changes in the threshold voltage Vt can cause significant changes in ID. Nevertheless, the changes are much less severe than if the source resistor RS were not present.The complicated expression for ID derived above does not suggest a straightforward approach forselecting values of VG and RS to achieve a target bias level. Furthermore, the voltage transfer characteristic for this circuit, even with a source degeneration resistor, is nonlinear. It is thereforedifficult to determine an optimum value to which the quiescent drain voltage VD and/or the quiescent drain current ID should be set. Because of the square-law nature of the relationship between ID and VGS, the output voltage swing is not symmetrical. In practice, many designers turnto a common rule of thumb in which the quiescent voltages across RD, the drain-source terminals of the MOSFET, and RS are simply each set equal to approximately one-third of VDD. That is,DDSDDSDDVRIVRI31,from which the values for RD and RS can be found directly if the nominal value of ID is specified. (The bias level of the drain current is often dictated by the desired value for the small-signal transconductance gm.) The appropriate value of the quiescent gate voltage VG can then be found by once again combining the relationships 221tGSnDVVkI  and SDGGSRIVV ,but this time solving for VG, which leads to .22212nDtSDGnDtSDGtSDGnDkIVRIVkIVRIVVRIVkIThe positive value of the square root is used because it corresponds to the requirement that VGS > Vt → VG − IDRS > Vt. Of course, this method for selecting the value of VG depends on knowing the values of kn and Vt, which vary considerably because of manufacturing tolerances 3 of 6and temperature effects. (The parameters n and Vt are especially sensitive to temperature.) For example, a typical range for Vt might be 1-3 V. It is therefore difficult, if not impossible, to set a quiescent drain current value that is repeatable from circuit to circuit. Bear in mind, however, that the presence of the source degeneration resistor RS will force the drain current to remain close to whatever value it happens to have. Thus, even though we cannot set ID to a specific valuewith much precision, we can make sure that it has negligible drift. In practice the nominal valuesof kn and Vt, obtained either


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