For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXA ExamplesSource files for examples demonstrating the use of VHDL are inthe /synopsys/syn/examples/vhdl directory. The examples are Moore Machine Mealy Machine Read–Only Memory (ROM) Waveform Generator Smart Waveform Generator Definable-Width Adder-Subtracter Count Zeros — Combinational Version Count Zeros — Sequential Version Soft Drink Machine — State Machine Version Soft Drink Machine — Count Nickels Version Carry-Lookahead Adder Serial-to-Parallel Converter — Counting Bits Serial-to-Parallel Converter — Shifting Bits Programmable Logic Array (PLA)VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXMoore MachineFigure A–1 is a diagram of a simple Moore finite-state ma-chine. It has one input (X), four internal states (S0 to S3), andone output (Z).Figure A–1 Moore Machine Specification S0 S1 S3 S2011001101010Present Next Outputstate state (Z)X=0 X=1 X=0 S0 S0 S2 0 S1 S0 S2 1 S2 S2 S3 1 S3 S3 S1 0The VHDL code implementing this finite-state machine isshown in Example A–1, which includes a schematic of thesynthesized circuit.The machine is described with two processes. One processdefines the synchronous elements of the design (state regis-ters); the other process defines the combinational part of thedesign (state assignment case statement). See the discussionunder ‘‘wait Statement” in Chapter 6 for more details onusing the two processes.VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXExample A–1 Implementation of a Moore Machineentity MOORE is –– Moore machine port(X, CLOCK: in BIT; Z: out BIT);end;architecture BEHAVIOR of MOORE is type STATE_TYPE is (S0, S1, S2, S3); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;begin –– Process to hold combinational logic COMBIN: process(CURRENT_STATE, X) begin case CURRENT_STATE is when S0 => Z <= ’0’; if X = ’0’ then NEXT_STATE <= S0; else NEXT_STATE <= S2; end if; when S1 => Z <= ’1’; if X = ’0’ then NEXT_STATE <= S0; else NEXT_STATE <= S2; end if; when S2 => Z <= ’1’; if X = ’0’ then NEXT_STATE <= S2; else NEXT_STATE <= S3; end if; when S3 => Z <= ’0’; if X = ’0’ then NEXT_STATE <= S3; else NEXT_STATE <= S1; end if; end case; end process;VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEX –– Process to hold synchronous elements (flip–flops) SYNCH: process begin wait until CLOCK’event and CLOCK = ’1’; CURRENT_STATE <= NEXT_STATE; end process;end BEHAVIOR;Example A-1 (continued) Implementation of a Moore MachineVHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXMealy MachineFigure A–2 is a diagram of a simple Mealy finite-state ma-chine. The VHDL code to implement this finite-state machineis shown in Example A–2. The machine is described in twoprocesses, like the previous Moore machine example.Figure A–2 Mealy Machine Specification S0 S2S10/11/11/00/01/10/01/00/0Present Next Outputstate state (Z) X=0 X=1 X=0X=1S0 S0 S2 0 1S1 S0 S2 0 0S2 S2 S3 1 0S3 S3 S1 0 1 S3VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXExample A–2 Implementation of a Mealy Machineentity MEALY is –– Mealy machine port(X, CLOCK: in BIT; Z: out BIT);end;architecture BEHAVIOR of MEALY is type STATE_TYPE is (S0, S1, S2, S3); signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;begin –– Process to hold combinational logic. COMBIN: process(CURRENT_STATE, X) begin case CURRENT_STATE is when S0 => if X = ’0’ then Z <= ’0’; NEXT_STATE <= S0; else Z <= ’1’; NEXT_STATE <= S2; end if; when S1 => if X = ’0’ then Z <= ’0’; NEXT_STATE <= S0; else Z <= ’0’; NEXT_STATE <= S2; end if; when S2 => if X = ’0’ then Z <= ’1’; NEXT_STATE <= S2; else Z <= ’0’; NEXT_STATE <= S3; end if; when S3 => if X = ’0’ then Z <= ’0’; NEXT_STATE <= S3; else Z <= ’1’;VHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEX NEXT_STATE <= S1; end if; end case; end process; –– Process to hold synchronous elements (flip–flops) SYNCH: process begin wait until CLOCK’event and CLOCK = ’1’; CURRENT_STATE <= NEXT_STATE; end process;end BEHAVIOR;Example A-2 (continued) Implementation of a Mealy MachineVHDL Compiler Reference V3.4For further assistance, email [email protected] or call your local support center HOME CONTENTS INDEXRead-Only Memory (ROM)Example A–3 shows how a ROM can be defined in VHDL. TheROM is defined as an array constant, ROM. Each line of theconstant array specification defines the contents of one ROMaddress. To read from the ROM, simply index into the array.The ROM’s number of storage locations and bit width can beeasily changed. The subtype ROM_RANGE specifies that theROM contains storage locations 0 to 7. The constantROM_WIDTH specifies that the ROM is five bits wide.After you define a ROM constant, you can index into thatconstant many times to read many values from the ROM. Ifthe ROM address is computable (see ‘‘Computable Oper-ands” in Chapter 5), no logic is built. The appropriate datavalue is simply inserted. If the ROM address is not comput-able, logic is built for each index into the value. For this rea-son, you need to consider resource sharing when using aROM (see Chapter 9, ‘‘Resource Sharing”). In the example,ADDR is not computable, so logic is synthesized to computethe value.VHDL Compiler does not actually instantiate a typical array-logic ROM, such as