Advanced Programmable Interrupt ControllersMultiple Logical ProcessorsRedirection Table EntryI/O APIC DocumentationOur ‘ioapic.c’ kernel-moduleOur ‘anchor’ systemsAdvanced Programmable Interrupt ControllersMultiprocessor-systems require enhanced circuitry for signaling of external interrupt-requestsDUAL CORE CPUMultiple Logical Processors CPU0CPU1I/OAPICLOCALAPICLOCALAPIC Advanced Programmable Interrupt Controller is needed to perform ‘routing’ of I/O requests from peripherals to CPUs(The legacy PICs are masked when the APICs are enabled)Redirection Table Entryreservedreserved interrupt vector L/PSTATUSH/LRIRRE/LMASK extended destination 63 56 55 48 32 destination 31 16 15 14 13 12 11 10 9 8 7 0 delivery mode 000 = Fixed001 = Lowest Priority010 = SMI 011 = (reserved)100 = NMI101 = INIT110 = (reserved)111 = ExtINTTrigger-Mode (1=Edge-triggered, 0=Level-triggered)Remote IRR (for Level-Triggered only) 0 = Reset when EOI received from Local-APIC 1 = Set when Local-APICs accept Level-Interrupt sent by IO-APICInterrupt Input-pin Polarity (1=Active-High, 0=Active-Low)Destination-Mode (1=Logical, 0=Physical)Delivery-Status (1=Pending, 0=Idle)I/O APIC Documentation“Intel I/O Controller Hub (ICH7) Family Datasheet” available online at http://www.intel.com/design/chipsets/datashts/307013.htmOur ‘ioapic.c’ kernel-module•This Linux module creates a pseudo-file (named ‘/proc/ioapic’) which lets users view the current contents of the I/O APIC Redirection-Table registers•You can compile and install this module for our classroom and CS Lab machines or our Core-2 Duo (“anchor”) machinesOur ‘anchor’ systemsMapping of IRQ-lines to Interrupt-ID numbers0 (masked) C (mouse) 0x891 (keyboard) 0x39 D ( ) 0x912 (timer) 0x31 E (hard-disk) 0x993 ( ) 0x41 F ( ) 0xA14 (serial-uart) 0x49 10 (ethernet) 0xA95 ( ) 0x51 11 ( ) 0xB16 (diskette-controller) 0x59 12 ( ) 0xB97 (parallel-port) 0x61 13 ( ) 0xC18 (real-time-clock) 0x69 14 (masked)9 (acpi) 0x71 15 (masked)A ( ) 0x79 16 (masked)B ( ) 0x81 17 ( )
View Full Document
Unlocking...