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Berkeley ELENG C149 - MicroBlaze Processor Reference Guide

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MicroBlaze Processor Reference GuideTable of ContentsAbout This GuideGuide ContentsConventionsTypographicalOnline DocumentMicroBlaze ArchitectureOverviewData Types and EndiannessInstructionsInstruction SummarySemaphore SynchronizationRegistersGeneral Purpose RegistersSpecial Purpose RegistersProgram Counter (PC)Machine Status Register (MSR)Exception Address Register (EAR)Exception Status Register (ESR)Branch Target Register (BTR)Floating Point Status Register (FSR)Exception Data Register (EDR)Process Identifier Register (PID)Zone Protection Register (ZPR)Translation Look-Aside Buffer Low Register (TLBLO)Translation Look-Aside Buffer High Register (TLBHI)Translation Look-Aside Buffer Index Register (TLBX)Translation Look-Aside Buffer Search Index Register (TLBS X)Processor Version Register (PVR)Pipeline ArchitectureThree Stage PipelineFive Stage PipelineBranchesMemory ArchitecturePrivileged InstructionsVirtual-Memory ManagementReal ModeVirtual ModeTranslation Look-Aside BufferAccess ProtectionUTLB ManagementRecording Page Access and Page ModificationReset, Interrupts, Exceptions, and BreakResetHardware ExceptionsBreaksInterruptUser Vector (Exception)Instruction CacheOverviewGeneral Instruction Cache FunctionalityInstruction Cache OperationInstruction Cache Software SupportData CacheOverviewGeneral Data Cache FunctionalityData Cache OperationData Cache Software SupportFloating Point Unit (FPU)OverviewFormatRoundingOperationsExceptionsSoftware SupportFast Simplex Link (FSL)Hardware Acceleration using FSLDebug and TraceDebug OverviewTrace OverviewMicroBlaze Signal Interface DescriptionOverviewFeaturesMicroBlaze I/O OverviewProcessor Local Bus (PLB) Interface DescriptionOn-Chip Peripheral Bus (OPB) Interface DescriptionLocal Memory Bus (LMB) Interface DescriptionLMB Signal InterfaceLMB TransactionsRead and Write Data SteeringFast Simplex Link (FSL) Interface DescriptionMaster FSL Signal InterfaceSlave FSL Signal InterfaceFSL TransactionsDirect FSL ConnectionsXilinx CacheLink (XCL) Interface DescriptionCacheLink Signal InterfaceCacheLink TransactionsDebug Interface DescriptionTrace Interface DescriptionMicroBlaze Core ConfigurabilityMicroBlaze Application Binary InterfaceData TypesRegister Usage ConventionsStack ConventionCalling ConventionMemory ModelSmall Data AreaData AreaCommon Un-Initialized AreaLiterals or ConstantsInterrupt and Exception HandlingMicroBlaze Instruction Set ArchitectureNotationFormatsInstructionsaddaddiandandiandnandnibeqbeqibgebgeibgtbgtiblebleibltbltibnebneibrbribrkbrkibsbsicmpfaddfrsubfmulfdivfcmpfltfintfsqrtgetgetdidivimmlbulbuilhulhuilwlwilwxmfsmsrclrmsrsetmtsmulmulhmulhumulhsumuliororipcmpbfpcmpeqpcmpneputputdrsubrsubirtbdrtidrtedrtsdsbsbisext16sext8shshisrasrcsrlswswiswxwdcwicxorxoriMicroBlaze Processor Reference GuideEmbedded Development Kit EDK 11.4UG081 (v10.3)MicroBlaze Processor Reference Guide www.xilinx.com UG081 (v10.3)Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.MicroBlaze Processor Reference Guide UG081 (v10.3)The following table shows the revision history for this document. Date Version Revision10/01/02 1.0 Xilinx EDK 3.1 release03/11/03 2.0 Xilinx EDK 3.2 release09/24/03 3.0 Xilinx EDK 6.1 release02/20/04 3.1 Xilinx EDK 6.2 release08/24/04 4.0 Xilinx EDK 6.3 release09/21/04 4.1 Minor corrections for EDK 6.3 SP1 release11/18/04 4.2 Minor corrections for EDK 6.3 SP2 release01/20/05 5.0 Xilinx EDK 7.1 release04/02/05 5.1 Minor corrections for EDK 7.1 SP1 release05/09/05 5.2 Minor corrections for EDK 7.1 SP2 release10/05/05 5.3 Minor corrections for EDK 8.1 release02/21/06 5.4 Corrections for EDK 8.1 SP2 release06/01/06 6.0 Xilinx EDK 8.2 release07/24/06 6.1 Minor corrections for EDK 8.2 SP1 release08/21/06 6.2 Minor corrections for EDK 8.2 SP2 release08/29/06 6.3 Minor corrections for EDK 8.2 SP2 release09/15/06 7.0 Xilinx EDK 9.1 release02/22/07 7.1 Minor corrections for EDK 9.1 SP1 release03/27/07 7.2 Minor corrections for EDK 9.1 SP2 releaseUG081 (v10.3) www.xilinx.com MicroBlaze Processor Reference Guide06/25/07 8.0 Xilinx EDK 9.2 release10/12/07 8.1 Minor corrections for EDK 9.2 SP2 release01/17/08 9.0 Xilinx EDK 10.1 release03/04/08 9.1 Minor corrections for EDK 10.1 SP1 release05/14/08 9.2 Minor corrections for EDK 10.1 SP2 release07/14/08 9.3 Minor corrections for EDK 10.1 SP3 release02/04/09 10.0 Xilinx EDK 11.1 release04/15/09 10.1 Xilinx EDK 11.2 release05/28/09 10.2 Xilinx EDK 11.3 release10/26/09 10.3 Xilinx EDK 11.4 releaseDate Version RevisionMicroBlaze Processor Reference Guide www.xilinx.com UG081 (v10.3)MicroBlaze Processor Reference Guide www.xilinx.com 5UG081 (v10.3)Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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