Slide 1Ideal 2-terminal MOS capacitor/diodeBand models (approx. scale)Flat band condition (approx. scale)Depletion for p-Si, Vgate> VFBDepletion for p-Si, Vgate> VFBEquivalent circuit for depletionInversion for p-Si Vgate>VTh>VFBInversion for p-Si Vgate>VTh>VFBApproximation concept “Onset of Strong Inv”MOS Bands at OSI p-substr = n-channelEquivalent circuit above OSIMOS surface states** p- substr = n-channeln-substr accumulation (p-channel)n-substrate depletion (p-channel)n-substrate inversion (p-channel)Values for gate work function, fmValues for fms with metal gateValues for fms with silicon gateTypical fms valuesFlat band with oxide charge (approx. scale)ReferencesEE 5340Semiconductor Device TheoryLecture 24 – Spring 2011Professor Ronald L. [email protected]://www.uta.edu/ronc©rlc L24-19Apr20112Ideal 2-terminalMOS capacitor/diodex-xox0SiO2silicon substrateVgateVsubconducting gate,area = LWtsub0yL©rlc L24-19Apr20113Band models (approx. scale)EoEcEvqcox ~ 0.95 eVmetal silicon dioxide p-type s/cqfm= 4.1 eV for AlEoEFmEFpEoEcEvEFiqfs,pqcSi= 4.05eVEg,ox~ 8 eV©rlc L24-19Apr20114Flat band condition (approx. scale)Ec,OxEvAlSiO2p-Siq(fm-cox)= 3.15 eVEFmEFpEcEvEFiq(cox-cSi)=3.1eVEg,ox~8eVcond band-flat forVVV8.0 VeV8.0EETheneV85.0EEIfsgMSfpfmFBfpfmfpcqffp= 3.95eV©rlc L24-19Apr20115Depletion for p-Si, Vgate> VFBSiO2p-type SiVgate> VFBVsub = 0EOx,x> 0x-xox0tsubx,OxSiOxSiSiSix,OxOxOxOxx,OxE31E39.37.11EE0xVEAcceptorsDepl Reg©rlc L24-19Apr20116Depletion forp-Si, Vgate> VFBFig 10.4b*©rlc L24-19Apr20117Equivalent circuitfor depletion•Depl depth given by the usual formula = xdepl = [2eSi(Vbb)/(qNa)]1/2•Depl cap, C’depl = eSi/xdepl•Oxide cap, C’Ox = eOx/xOx•Net C is the series combOxdepltot'C1'C1'C1C’OxC’depl©rlc L24-19Apr20118Inversion for p-SiVgate>VTh>VFBVgate> VFBVsub = 0EOx,x> 0inversion for threshold above E Induced depletes 0 E Induced 0xVESiSiOxOxx,Ox--AcceptorsDepl Reg e- e- e- e- e-©rlc L24-19Apr20119Inversion for p-SiVgate>VTh>VFBFig 10.5*©rlc L24-19Apr201110Approximation concept“Onset of Strong Inv”•OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh•Assume ns = 0 for VG < VTh•Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh •Cd,min = eSi/xd,max for VG > VTh •Assume ns > 0 for VG > VTh©rlc L24-19Apr201111MOS Bands at OSIp-substr = n-channelFig 10.9*©rlc L24-19Apr201112Equivalent circuitabove OSI•Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2•Depl cap, C’d,min = eSi/xd,max•Oxide cap, C’Ox = eOx/xOx•Net C is the series combOx,mindtot'C1'C1'C1C’OxC’d,min©rlc L24-19Apr201113MOS surface states**p- substr = n-channelVGSsSurf chg Carr DenVGS < VFB < 0s < 0 Accum. ps > NaVGS = VFB < 0s = Neutral ps = NaVFB < VGSs > 0 Depletion ps < NaVFB < VGS < VThs = |p| I ntrinsic ns = ps = niVGS < VThs > |p| Weak inv ni< ns < NaVGS = VThs = 2|p| O.S.I . ns = Na©rlc L24-19Apr201114n-substr accumulation (p-channel)Fig 10.7a*©rlc L24-19Apr201115n-substrate depletion(p-channel)Fig 10.7b*©rlc L24-19Apr201116n-substrate inversion(p-channel)Fig 10.7*©rlc L24-19Apr201117Values for gate workfunction, fmV 17.5q/E :Si-poly pV 05.4 :Si-poly nV 55.4 :W ,TungstenV 65.5 :Pt ,PlatinumV 6.4 :Mo ,MolybdenumV 1.5 :Au ,GoldV 28.4 :Al ,umminAlugSimSimmmmmm©rlc L24-19Apr201118Values for fmswith metal gate02586.0V ,12.1E ,19E8.2N10E45.1n ,05.4 ,28.4NNlnV :Si-n to AlnNlnVq2EnNNlnV :NotenNNlnV :Si-p to AltgCiSiAlm,dCtSiAlm,msiatg2iaCt2iaCtSiAlm,ms©rlc L24-19Apr201119Values for fmswith silicon gateidtgdCtdCtSigSimsiatg2iaCt2iaCtSiSimsnNlnVq2ENNlnV :NoteNNlnVqE :Si-n to poly pnNlnVq2EnNNlnV :NotenNNlnV :Si-p to poly n©rlc L24-19Apr201120Fig 10.15*fms(V)NB (cm-3)Typical fms values©rlc L24-19Apr201121Flat band with oxidecharge (approx. scale)EvAlSiO2p-SiEFmEc,OxEg,ox~8eVEFpEcEvEFi'Ox'ssmsOxmsFBOxOxcOx'ssxssmssCQVVxVdxdEq1QEsurface gate the onis Q'Q' chargea cond FB at thenbound, Ox/Si the atis Q' charge a Ifq(ffp-cox)q(Vox)q(fm-cox)q(VFB)VFB= VG-VB, when Si bands are flatEx+<--Vox-->-©rlc L24-19Apr201122References* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York,
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