TMS320x2833x, 2823x System Control and InterruptsTable of ContentsPreface1 Flash and OTP Memory1.1 Flash Memory1.2 OTP Memory2 Flash and OTP Power Modes2.1 Flash and OTP Performance2.2 Flash Pipeline Mode2.3 Reserved Locations Within Flash and OTP2.4 Procedure to Change the Flash Configuration Registers3 Flash and OTP Registers4 Code Security Module (CSM)4.1 Functional Description4.2 CSM Impact on Other On-Chip Resources4.3 Incorporating Code Security in User Applications4.3.1 Environments That Require Security Unlocking4.3.2 Password Match Flow4.3.3 Unsecuring Considerations for Devices With/Without Code Security4.3.3.1 C Code Example to Unsecure4.3.3.2 C Code Example to Resecure4.4 Do's and Don'ts to Protect Security Logic4.4.1 Do's4.4.2 Don'ts4.5 CSM Features - Summary5 Clocking and System Control5.1 Clocking5.1.1 Enabling/Disabling Clocks to the Peripheral Modules5.2 OSC and PLL Block5.2.1 PLL-Based Clock Module5.2.2 Main Oscillator Fail Detection5.2.3 XCLKOUT Generation5.2.4 PLL Control (PLLCR) Register5.2.5 PLL Control, Status and XCLKOUT Register Descriptions5.2.6 External Reference Oscillator Clock Option5.3 Low-Power Modes Block5.4 Watchdog Block5.4.1 Servicing The Watchdog Timer5.4.2 Watchdog Reset or Watchdog Interrupt Mode5.4.3 Watchdog Operation in Low Power Modes5.4.4 Emulation Considerations5.4.5 Watchdog Registers5.5 32-Bit CPU Timers 0/1/26 General-Purpose Input/Output (GPIO)6.1 GPIO Module Overview6.2 Configuration Overview6.3 Digital General Purpose I/O Control6.4 Input Qualification6.4.1 No Synchronization (asynchronous input)6.4.2 Synchronization to SYSCLKOUT Only6.4.3 Qualification Using a Sampling Window6.5 GPIO and Peripheral Multiplexing (MUX)6.6 Register Bit Definitions7 Peripheral Frames7.1 Peripheral Frame Registers7.2 EALLOW-Protected Registers7.3 Device Emulation Registers7.4 Write-Followed-by-Read Protection8 Peripheral Interrupt Expansion (PIE)8.1 Overview of the PIE Controller8.1.1 Interrupt Operation Sequence8.2 Vector Table Mapping8.3 Interrupt Sources8.3.1 Procedure for Handling Multiplexed Interrupts8.3.2 Procedures for Enabling And Disabling Multiplexed Peripheral Interrupts8.3.3 Flow of a Multiplexed Interrupt Request From a Peripheral to the CPU8.3.4 The PIE Vector Table8.4 PIE Configuration Registers8.5 PIE Interrupt Registers8.5.1 PIE Interrupt Flag Registers8.5.2 PIE Interrupt Enable Registers8.5.3 CPU Interrupt Flag Register (IFR)8.5.4 Interrupt Enable Register (IER) and Debug Interrupt Enable Register (DBGIER)8.6 External Interrupt Control RegistersAppendix A Revision HistoryTMS320x2833x, 2823x System Control andInterruptsReference GuideLiterature Number: SPRUFB0DSeptember 2007–Revised March 20102SPRUFB0D–September 2007–Revised March 2010Submit Documentation FeedbackCopyright © 2007–2010, Texas Instruments IncorporatedPreface ....................................................................................................................................... 91 Flash and OTP Memory ...................................................................................................... 121.1 Flash Memory .......................................................................................................... 121.2 OTP Memory ........................................................................................................... 122 Flash and OTP Power Modes .............................................................................................. 122.1 Flash and OTP Performance ......................................................................................... 142.2 Flash Pipeline Mode ................................................................................................... 152.3 Reserved Locations Within Flash and OTP ........................................................................ 162.4 Procedure to Change the Flash Configuration Registers ......................................................... 163 Flash and OTP Registers .................................................................................................... 184 Code Security Module (CSM) .............................................................................................. 234.1 Functional Description ................................................................................................. 234.2 CSM Impact on Other On-Chip Resources ......................................................................... 264.3 Incorporating Code Security in User Applications ................................................................. 274.4 Do's and Don'ts to Protect Security Logic .......................................................................... 324.5 CSM Features - Summary ............................................................................................ 325 Clocking and System Control .............................................................................................. 325.1 Clocking ................................................................................................................. 325.2 OSC and PLL Block ................................................................................................... 405.3 Low-Power Modes Block .............................................................................................. 485.4 Watchdog Block ........................................................................................................ 495.5 32-Bit CPU Timers 0/1/2 .............................................................................................. 556 General-Purpose Input/Output (GPIO) .................................................................................. 606.1 GPIO Module Overview ............................................................................................... 606.2 Configuration Overview ............................................................................................... 666.3 Digital General Purpose I/O Control ................................................................................. 676.4 Input Qualification ...................................................................................................... 686.5 GPIO and Peripheral Multiplexing (MUX) ........................................................................... 736.6 Register Bit Definitions