Spartan-3E FPGA Starter Kit Board User GuideTable of ContentsAbout This GuideAcknowledgementsGuide ContentsAdditional ResourcesIntroduction and OverviewChoose the Starter Kit Board for Your NeedsSpartan-3E FPGA Features and Embedded Processing FunctionsAdvanced Spartan-3 Generation Development BoardsKey Components and FeaturesDesign Trade-OffsConfiguration Methods Galore!Voltages for all ApplicationsRelated ResourcesSwitches, Buttons, and KnobSlide SwitchesLocations and LabelsOperationUCF Location ConstraintsPush-Button SwitchesLocations and LabelsOperationUCF Location ConstraintsRotary Push-Button SwitchLocations and LabelsOperationUCF Location ConstraintsDiscrete LEDsLocations and LabelsOperationUCF Location ConstraintsRelated ResourcesClock SourcesOverviewClock ConnectionsVoltage Control50 MHz On-Board OscillatorAuxiliary Clock Oscillator SocketSMA Clock Input or Output ConnectorUCF ConstraintsLocationClock Period ConstraintsRelated ResourcesFPGA Configuration OptionsConfiguration Mode JumpersPROG Push ButtonDONE Pin LEDProgramming the FPGA, CPLD, or Platform Flash PROM via USBConnecting the USB CableProgramming via iMPACTProgramming Platform Flash PROM via USBRelated ResourcesCharacter LCD ScreenOverviewCharacter LCD Interface SignalsVoltage CompatibilityInteraction with Intel StrataFlashUCF Location ConstraintsLCD ControllerMemory MapCommand SetOperationFour-Bit Data InterfaceTransferring 8-Bit Data over the 4-Bit InterfaceInitializing the DisplayWriting Data to the DisplayDisabling the Unused LCDRelated ResourcesVGA Display PortSignal Timing for a 60 Hz, 640x480 VGA DisplayVGA Signal TimingUCF Location ConstraintsRelated ResourcesRS-232 Serial PortsOverviewUCF Location ConstraintsPS/2 Mouse/Keyboard PortKeyboardMouseVoltage SupplyUCF Location ConstraintsDigital to Analog Converter (DAC)SPI CommunicationInterface SignalsDisable Other Devices on the SPI Bus to Avoid ContentionSPI Communication DetailsCommunication ProtocolSpecifying the DAC Output VoltageDAC Outputs A and BDAC Outputs C and DUCF Location ConstraintsRelated ResourcesAnalog Capture CircuitDigital Outputs from Analog InputsProgrammable Pre-AmplifierInterfaceProgrammable GainSPI Control InterfaceUCF Location ConstraintsAnalog to Digital Converter (ADC)InterfaceSPI Control InterfaceUCF Location ConstraintsDisable Other Devices on the SPI Bus to Avoid ContentionConnecting Analog InputsRelated ResourcesIntel StrataFlash Parallel NOR Flash PROMStrataFlash ConnectionsShared ConnectionsCharacter LCDXilinx XC2C64A CPLDSPI Data LineUCF Location ConstraintsAddressDataControlSetting the FPGA Mode Select PinsRelated ResourcesSPI Serial FlashUCF Location ConstraintsConfiguring from SPI FlashSetting the FPGA Mode Select PinsCreating an SPI Serial Flash PROM FileDownloading the Design to SPI FlashDownloading the SPI FlashAdditional Design DetailsShared SPI Bus with PeripheralsOther SPI Flash Control SignalsVariant Select Pins, VS[2:0]Jumper Block J11Programming Header J12Multi-Package LayoutRelated ResourcesDDR SDRAMDDR SDRAM ConnectionsUCF Location ConstraintsAddressDataControlReserve FPGA VREF PinsRelated Resources10/100 Ethernet Physical Layer InterfaceEthernet PHY ConnectionsMicroBlaze Ethernet IP CoresUCF Location ConstraintsRelated ResourcesExpansion ConnectorsHirose 100-pin FX2 Edge Connector (J3)Voltage Supplies to the ConnectorConnector Pinout and FPGA ConnectionsCompatible BoardMating Receptacle ConnectorsDifferential I/OUCF Location ConstraintsSix-Pin Accessory HeadersHeader J1Header J2Header J4UCF Location ConstraintsConnectorless Debugging Port Landing Pads (J6)Related ResourcesXC2C64A CoolRunner-II CPLDUCF Location ConstraintsFPGA Connections to CPLDCPLDRelated ResourcesDS2432 1-Wire SHA-1 EEPROMUCF Location ConstraintsRelated ResourcesSchematicsFX2 Expansion Header, 6-pin Headers, and Connectorless Probe HeaderRS-232 Ports, VGA Port, and PS/2 PortEthernet PHY, Magnetics, and RJ-11 ConnectorVoltage RegulatorsFPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG ConnectionsFPGA I/O Banks 0 and 1, OscillatorsFPGA I/O Banks 2 and 3Power Supply DecouplingXC2C64A CoolRunner-II CPLDLinear Technology ADC and DACIntel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAMButtons, Switches, Rotary Encoder, and Character LCDDDR SDRAM Series Termination and FX2 Connector Differential TerminationExample User Constraints File (UCF)RSpartan-3E FPGA Starter Kit Board User GuideUG230 (v1.2) January 20, 2011Spartan-3E FPGA Starter Kit Board User Guide www.xilinx.com UG230 (v1.2) January 20, 2011Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. 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