THE PENNSYLVANIA STATE UNIVERSITY Wilkes-Barre Campus ELECTRICAL ENGINEERING TECHNOLOGY PROGRAM EET 331: ELECTRONIC DESIGN LABORATORY REPORT Experiment #02: DESIGN WITH OPERATIONAL AMPLIFIERS Date Performed: January 30, 2008 Due Date: February 13, 2008 Author(s): Christopher Moses TABLE OF CONTENTS Subject Page(s) Introduction: 1 Experiment Development and Results: 2-5 Conclusion and Discussion: 6 Appendix: 7 INTRODUCTION: Experiment 02 design with operational amplifiers implemented the following goals. Using a single operational amplifier design a non-inverting voltage amplifier with a calculated input impedance greater than 20 kΩ, and a variable gain between 0.5 and 15. Analyze the circuit using theoretical hand calculations and circuit simulating software. Build the circuit given tools and components provided in the laboratory. Compare the calculated predictions with the laboratory results. Experiment 02 showed that a greater level of understanding about operational amplifiers and combination circuits was needed in order to design a circuit given specifications instead of a schematic. Design was a process of implementing ideas, testing and troubleshooting those ideas and then perfecting or changing them based on the results. Experiment 02 was included in the course to increase the student’s knowledge of operational amplifiers and combination circuits. To teach students to use the knowledge and skills they have gained to implement their own ideas, instead of staying with in the confines of the textbook. To teach students that not every idea will be designed, analyzed and tested perfectly the first time every time.EXPERIMENT DEVELOPMENT AND RESULTS: The circuit as shown in figure 1 met all the design specifications given in experiment 02. Figure 1: Non-inverting variable voltage amplifier circuit The circuit utilized a single operational amplifier and passive components to provide a non-inverted voltage output. The circuit provided voltage amplification with a variable gain between 0.5 and 15. The circuit had an input impedance greater than 20 kΩ. Testing and troubleshooting was done with a multimeter, oscilloscope, and a variable DC input voltage source unless otherwise specified. The theoretical gain of the circuit was calculated using the gain equation ⎟⎟⎠⎞⎜⎜⎝⎛+=34221RRvvinout. For the derivation of the gain equation see appendix. The theoretical calculated gain at the extremes of the potentiometer was .5 when pot = 0 Ω and 15 when pot = 50 kΩ. The hand calculations were verified using Multisim as shown in figures 2 and 3.Figure 2: Gain of the circuit when potentiometer = 0 Ω Figure 3: Gain of the circuit when potentiometer = 50 kΩ The laboratory measured gain at the extremes of the potentiometer was .5 when pot = 0 Ω and 15.2 when pot = 50 kΩ. The measured input impedance of the circuit was 48.8 kΩ, which exceeded the minimum 20 kΩ specified in experiment 02. The DC gain of the circuit was set to 10, and the input voltage was changed to a sinusoidal signal at 1 kHz. A gain of 10 for the circuit with AC input voltage was verified as shown in figure 4. Figure 4: Gain of 10 with AC input voltage The sinusoidal input voltage was increased so that the output voltage exceed the maximum output voltage that the operational amplifier could supply. The measured positive clipped voltage was 14.5 volts, and the measured negative clipped voltage was -14 volts as shown in figure 5.Figure 5: Positive and negative clipped voltages The input voltage was reduced so that the output voltage was around 10 volts peak-to-peak. The frequency was varied from 1 kHz to 500 kHz in varying increments. From the oscilloscope display the output voltage magnitudes and phase angles in microseconds were recorded in table 1. The phase angles in microseconds were converted into angles in degrees, using the equation °×Δ= 360Ttθ where ∆t is the time difference between the input and output waveforms and T is the period of the input voltage. The phase angle in degrees were recorded into table 1. Table 1: Gain magnitude and phase angle vs. frequencyThe gain magnitude and gain phase angle as they vary with frequency are graphically represented in graphs 1 and 2 respectfully. Gain Magnitude vs Frequency0.002.004.006.008.0010.0012.000 100 200 300 400 500 600Frequency (kHz)Gain Magnitude (V)Gain Magnitude vs Frequency Graph 1: Gain magnitude vs. frequency Phase Angle vs. Frequency0204060801001201400 100 200 300 400 500 600Frequency (kHz)Phase Angle (degrees)Phase Angle vs. Frequency Graph 1: Gain phase angle magnitude vs. frequencyCONCLUSION AND DISCUSSION: Using a single operational amplifier a non-inverting voltage amplifier was designed with a calculated input impedance greater than 20 kΩ, and a variable gain between 0.5 and 15. Analyze the circuit using theoretical hand calculations and circuit designing software. Build the designed circuit given tools and components provided in the laboratory. Compare the calculated predictions with the measured laboratory results. The laboratory gain measurements matched the mathematical and the simulated results within an expectable margin of error. The output of the non-inverting variable voltage amplifier was able to adjust the gain from 0.5 to 15 by varying the single potentiometer. The measured gain was higher than the calculated gain, because the potentiometer was not ideal and its resistance slightly exceeded 50 kΩ resulting in a gain greater than 15. These results verified the amplifiers output equation. The non-inverting variable voltage amplifier did not work perfectly for high frequencies. The gain voltage magnitude decreased as the frequency increased. The gain phase angle increased as the frequency increased. This was most likely caused by the slew rate of the operational amplifiers that compose the non-inverting variable voltage amplifier. The slew rate is how fast the output of the operational amplifier can change in accordance with a change of the input signal. Electrons can only flow so fast across the pnp junctions of the bipolar transistors that make up the operational amplifiers. When the input frequency exceeded this flow rate the transistors would saturated and the output could not keep up with the input voltage as shown in tables 1and 2. Designing a circuit