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IM Reg IM DM Reg Reg DM Reg 0 1 2 IM Reg IM DM 1 1 8 DM Reg Reg Reg 1 3 43 50 1 67 0 1 60 1 9 1 IM Reg DM Reg 1 8 DM Reg Reg IM 1 9 9 1 1 1 IM Reg IM DM 8 Reg Reg IM DM Reg Reg DM Reg 67 1 1 IM Reg DM IM Reg Reg IM IM 8 DM Reg Reg Reg DM Reg 4 3 43 0 1 2 IM Reg IM DM 8 Reg Reg IM DM Reg Reg DM IM Reg Reg DM Reg 1 1 Reg DM Reg B5 Reg C B5 C 5 B IM DM 5 B Reg 5 IM 5 A 4 53 43 10 4 53 43 1 A 9 54 1 4 53 43 1 8 0 B5 Reg Reg C DM Reg B5 IM Reg 5 B DM 5 Reg 5 IM 5 1 C 4 5 B 0 9 54 3 A 9 54 1 A 9D59 1 9 54 1 A 9D59 1 PC Write IF ID Write ID EX MemRead Hazard Unit Rs ID EX Rt 0 0 1 Control PC Addr IF ID Read register 1 Instr Read data 1 Read register 2 Write register Instruction memory Write data Read data 2 Registers ID EX RegisterRt EX MEM WB M WB MEM WB EX M WB 0 1 2 ALUSrc 0 1 2 Result 0 RegDst Extend Address Data memory 1 Instr 15 0 Rt ALU Zero Write Read data data 1 0 0 Rd 1 Rs EX MEM RegisterRd Forwarding Unit MEM WB RegisterRd E 9D59 1 9 54 3 60 1 9D59 1 9 54 1 F 0 1 1 1 1 9D59 0 B 4 B 3 43 50 1 1 0 IM Reg 9D G 0 Reg DM 9 4 3 B 3 4 1 8 E 8 9D 0 5 1 9 4 3 3 0 9D 9 4 3 3 0 9D 9 9 4 3 3 0 1 1 0 PCSrc Control IF ID 4 ID EX WB EX MEM M WB MEM WB EX M WB Add P C Add RegWrite Read Instruction 31 0 address Instruction memory Read register 1 Read data 1 Read register 2 Read data 2 Write register Write data Instr 15 0 Instr 20 16 Instr 15 11 Shift left 2 ALU 0 MemWrite Zero Result 1 ALUOp Registers Data memory Write data ALUSrc Sign extend Address RegDst MemToReg Read data 1 MemRead 0 0 1 3 1 4 1 1 67 H 1 1 4 1 8 B 1 6 IM Reg DM Reg IM 1 1 6 IM Reg G I DM Reg IM Reg 8 DM Reg 9 I 9 F B 1 1 6 IM Reg IM DM Reg IM Reg DM Reg 8 Reg DM Reg 9 1 1 B 0 1 B 1 1 1 1 6 6 IM Reg IM DM Reg IM Reg 8 DM Reg Reg IM 3 1 I 1 1 F7 F7 3 1 1 1 2 1 0 1 1 8 0 0 9 4 4J 9 1 1 6 IM Reg DM 8 DM Reg Reg IM IM Reg 0 4J 9D 1 9D 1 1 0 1 3 9FK 1 9D59 D 1 1 2 1 9D D 1 B 1 1 E 1 ID EX 0 EX MEM WB IF ID Control PCSrc M WB MEM WB EX M WB 4 Add P C I Shift left 2 Read register 1 Addr Instr Read register 2 Write register Instruction memory IF Flush Read data 1 Write data Extend ALU Zero ALUSrc Read data 2 0 Registers 1 Result Data memory RegDst Rt Rd Address Write Read data data 1 0 0 1 K 1 B 1 1 1 1 1 1 1 1 G 6 2 B 0 0 1 F7 1


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U of I CS 232 - Lecture notes

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