Page 1 San Jose State University Department of Electrical Engineering EE270 - Advanced Logic Design Instructor: Tri Caohuu Office Location: ENGR 375 Telephone: (408) 924-3951 Email: [email protected] Office Hours: Monday, Wednesday 14:30 to 17:00 Class Days/Time: MW 18:00-19:15 Class Room: E329 Laboratory: Open Lab E389/E291 Course Description: This course presents principles and techniques in logic design: design and analysis of combinational logic circuit; flip-flop properties, sequential circuit analysis and synthesis, algorithmic state machines; asynchronous circuit design and analysis; and design for testability. The students are required to do exercises and a design project in the open laboratory using HDL-based methodology. The course is intended for senior students and beginning graduate student in the digital design concentration. Course Goals and Student Learning Objectives: This course aims at providing students with fundamentals concepts and design techniques in synchronous circuit design, asynchronous circuit design and design for testability. Students will firstly learn to analyze and synthesize synchronous digital circuits including techniques to reduce of state table and to make optimal state assignment. In the second part students will learn both Huffman and Muller types of asynchronous circuit and will be introduced to asynchronous design techniques. In the final part, students will be introduce to fundamentals and techniques in design for testability (DFT) Course Content Learning Outcomes: Upon successful completion of this course, students will be able to: 1. CLO1:Understand fundamental concepts of synchronous circuit design (a) 2. CLO2: Perform simplification of switching functions (c)Page 2 3. CLO3: Analyze and synthesize synchronous circuits (e) 4. CLO5: Understand the classification of asynchronous circuit (a) 5. CLO6: Analyze and synthesize fundamental asynchronous circuit design (e) 6. CLO7: Demonstrate the ability to use HDL for modeling and verification purposes (k) 7. CLO8: Demonstrate the ability design and test certain class of synchronous and asynchronous circuits (c) 8. CLO9: Understand fundamental concepts and practices of DFT(a) 9. CLO10: Using CAD tools to design, verify, and implementation of advanced logic circuits (k) ABET outcomes The letters in parentheses in the course learning objectives refer to ABET criterion 3 outcomes satisfied by the course. These are listed below as a reference: (a) An ability to apply knowledge of mathematics, science, and engineering (b) An ability to design and conduct experiments, as well as to analyze and interpret data (c) An ability to design a system, component, or process to meet desired needs (d) An ability to function on multi-disciplinary teams (e) An ability to identify, formulate, and solve engineering problems (f) An understanding of professional and ethical responsibility (g) An ability to communicate effectively (h) The broad education necessary to understand the impact of engineering solutions in a global and societal context (i) A recognition of the need for, and an ability to engage in life-long learning (j) A knowledge of contemporary issues (k) An ability to use the techniques, skills, and modern engineering tools necessary for engineering practicePage 3 (l) Specialization in one or more technical specialties that meet the needs of companies (m) Knowledge of probability and statistics, including applications to electrical engineering (n) Knowledge of advanced mathematics, including differential and integral equations, linear algebra, complex variables, and discrete mathematics (o) Basic sciences, computer science, and engineering sciences necessary to analyze and design complex electrical and electronic devices, software, and systems containing hardware and software components Text: Digital Logic Circuit Analysis and Design, V. P. Nelson, H. T. Nagle, B. D. Carroll, J. D. Irwin, H Prentice Hall 1995 Reference Texts: 1. Digital Principles and Design, Donald Givone McGrawHill 2003 2. Contemporary Logic Design, Randy h. Katz and Gaetano Borriello, Prentice Hall 2005 3. Asynchronous Circuit Design, Chris J. Myers, Prentice Hall 2001 Grading policy: Midterm 1 15% Midterm 2 20% Projects 25% Final Exam 40% Special Homework 5% Bonus points Note: Final Exam is on Wed May 19 from 17:15 to 19:30 Course Outline: I. Introduction [Week 1 and 2]  Review of switching algebra  Analysis and synthesis of combinational logic  Synchronous vs asynchronous circuits  HDL toolsPage 4 II. Simplification of switching functions [Week 3 and 4]  Karnaugh Maps  Quine-McCluskey method  Espresso Algorithm III. Synchronous circuit design [Week 5, 6, 7, 8]  Sequential devices  Analysis and synthesis of synchronous sequential circuits  Simplification and Optimization of Sequential Circuit IV. Asynchronous sequential circuits [Week 10, 11, 12,13]  Huffman Circuit  Muller Circuit  Timed Circuit  Petri-net and Graph-based Methods  Transformation Methods  Asynchronous data path (pipelines)  Verification V. Introduction to design for testability [Week 14,15]  Fault models  Combinational circuit testing  Sequential logic circuit  DFT  BIST VI. Design Project Note: Week 9 is for review and midtermPage 5 University Policies Academic integrity Students should know that the University’s Academic Integrity Policy is availabe at http://www.sa.sjsu.edu/download/judicial_affairs/Academic_Integrity_Policy_S07-2.pdf. Your own commitment to learning, as evidenced by your enrollment at San Jose State University and the University’s integrity policy, require you to be honest in all your academic course work. Faculty members are required to report all infractions to the office of Student Conduct and Ethical Development. The website for Student Conduct and Ethical Development is available at http://www.sa.sjsu.edu/judicial_affairs/index.html. Instances of academic dishonesty will not be tolerated. Cheating on exams or plagiarism (presenting the work of another as your own, or the use of another person’s ideas without giving proper credit) will result in a failing grade and sanctions by the University. For this class, all assignments are to be