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UCD ECS 201A - Study Notes

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Very Short Answer:(1) (1) Peak performance does or does not track observed performance.(2) (1) Which is more effective,dynamic or static branch prediction?(3) (1) Do benchmarks remain valid indefinitely?(4) (2) Issuing multiple instructions per cycle puts tremendous pressure on what twoparts of themachine?(5) (2) In class we mentioned VLIW and Superscalar as twoways to circumvent the Flynn Limit of 1.We also talked about twoother approaches - what were they?(6) (2) Out of Order completion makes supporting what very difficult?(7) (2) Decoupled architectures split a program into twostreams. What are they?(8) (2) Are wire delays or transistors more likely to be the most significant limit on clock frequencyinthe future? Why?(9) (2) What is Amdahl’slaw (in words)?(10) (2) What is the relationship between speculation and power consumption?-1-Short Answers:(10) (3) What is the primary difference between Scoreboarding and Tomasulo’salgorithm? What hard-ware feature makes Tomasulo’swork?(11) (3) Whyare there multiple dies per silicon wafer? Whynot just fabricate one huge die per wafer?(12) (3) The book lists several things that limit the amount of achievable ILP.List 3 of them.(13) (4) Understanding the hardware can influence howyou write programs. Give atleast 2 examples ofhowyou might write software differently for a heavily pipelined machine verses a non-pipelinedone.-2-(14) (4)What is a predicated instruction? What are the advantages to using predicated instructions?When would you not want to use one?(15) (4) What is the definition of a basic block? Whyisthere a desire to create larger ones?(16) (3) There are at least twotypes of control flowchanges that standard dynamic branch predictorshave trouble with. There is a technique that works well for one of these types ... name the twotypesof branches, and the technique used to successfully deal with one of them.(17) (4) Supporting precise interrupts in machines that allowout of order completion is a challenge.Briefly explain why, and give three different techniques that can be used to provide precise inter-rupts.-3-(18) (5) Whyisbranch prediction important? What performance enhancing techniques have made it so?List 3 examples of existing Branch Prediction strategies in order of (average) increasing effec-tiveness.(19) (5) What does SMT stand for? What is SMT trying to accomplish? What is the difference betweenSuperscalar,coarse MT,fine MT,and SMT?(20) (6) Compare and contrast Superscalar and VLIW.Describe each, and list the advantages and disad-vantages of each approach.-4-(21) (10) Drawabasic high-levelpicture of what tomasulo’shardware looks like, when the ROB isincluded. (In other words, sketch out all the hardware involved, and howthings are connected.) Theemphasis is on conveying knowledge - do not worry about howpretty it is, but do makesure I canread it and understand what you have done.-5-(22) (10) Youare giventhe following code sequence:ADDF F1,F2,F3SUBF F1,F4,F5MULTF F2,F6,F7DIVF F1,F8,F9Assume there are 8 logical and 16 physical registers. On the left belowisthe register mapping uponentering the code sequence. Your job is to fill in the mappings after the execution of the DIVFinstruction, including what is on the free list. (Assume that during the execution of this code, noregisters are released - in other words, the free list will be shorter at the end than at the beginning.)BEFORELogical Physical0214263841051261470Free Pool: 0,2,4,9,10,13,14,15AFTERLogical Physical01234567Free Pool:Now, rewrite the code sequence belowusing the actual physical register names instead of the logicalones.ADDF P__,P__,P__SUBF P__,P__,P__MULTF P__,P__,P__DIVF P__,P__,P__-6-(23) (15) Giventhe following loop:LOOP: LoadF0,0($1)AddF4,F0,F2StoreF4,0(F1)SubR1,R1,#4BneR1,R2,LoopThere is a 1 cycle Load Delay Slot, a 1 cycle Branch Delay Slot, and a 2 cycle Add Delay Slot.Your machine has 16 registers.a) Calculate howmanycycles this loop requires in order to execute 9 times.b) Nowunroll the loop 3 times, schedule the code, and calculate howmanycycles your unrolled,scheduled loop requires to execute.-7-(24) (4) In class, we talked about the cycle by cycle steps that occur on different interrupts. Forexample,here is what happens if there is an illegaloperand interrupt generated by instruction i+1:123456789iIFIDEXMEM WBi+1 IF ID EX MEM WB <- Interrupt detectedi+2 IF ID EX MEM WB <- Instruction Squashedi+3 IF ID EX MEM WB <- Trap Handler fetchedi+4 IF ID EX MEM WBFill out the following table if instruction i+1 experiences a fault in the EX stage:12345678910iIFIDEXMEM WBi+1 IF ID EX MEM WBi+2 IF ID EX MEM WBi+3 IF ID EX MEM WBi+4 IF ID EX MEM WBi+5 IF ID EX MEM WBWhat happens in this case?12345678910iIFIDEXMEM WB <- Data write causes Page Faulti+1 IF ID EX MEM WB <- Divide by Zeroi+2 IF ID EX MEM WB <- IllegalOpcodei+3 IF ID EX MEM WBi+4 IF ID EX MEM WBi+5 IF ID EX MEM


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UCD ECS 201A - Study Notes

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