Simulation Using WinSPICEDavid W. GrahamLane Department of Computer Science and Electrical EngineeringWest Virginia University© David W. Graham 20072Why Simulation? • Theoretical calculations only go so far…• Find out the circuit behavior in a variety of operating conditions• It is currently the best way of designing a circuit (industry standard)• Provides intuitive “feel” for circuit operation (without requiring expensive equipment)3Simulator OptionsWide variety of circuit simulators• Specialized simulators (typically discrete-time)– Multitude of digital simulators– Switcap (for switched-capacitor circuits)• Generic simulators (analog / continuous-time circuits typically use these)– SPICE (Simulation Program with Integrated Circuit Emphasis)4SPICE Options Available at WVU•HSPICE– Good– Expensive– Different syntax •PSPICE– Schematic capture– Node limitation (9 nodes maximum)• WinSPICE– Free! (Plus, it is good in many other ways)5WinSPICEPros•Free•Small Size• Can run it from MATLAB• Works well• No node limitations• Can use the EKV model (good for subthreshold simulations)• Works in WindowsCons• No schematic capture (Rumor – XCircuit can perform schematic capture)• Only works in Windows• (Occasional convergence problems – but improving)6How to Obtain WinSPICE• Free download• www.winspice.com• Go to “Download”– Download “Current Full Version”– Then, download the current stable release (this is simply an update)7Writing SPICE Decks / NetlistsSPICE Deck/Netlist is a text description of a circuitConsists of the following parts• Header• Circuit connections• Subcircuit descriptions (if needed)• Model descriptions (if needed – usually only for transistors)• Analyses to be performed• Outputs to be saved / displayed8Basic Circuit Elements• Resistor R<label> node1 node2 value• Capacitor C<label> node1 node2 value• Inductor L<label> node1 node2 valueExamplesR1 1 2 100 CIN IN OUT 0.1u12R1= 100ΩinoutCin= 0.1µFSignifies resistorResistor “name”Signifies “micro” (1e-6)Nodes can be signified by words instead of numbers9Independent Voltage and Current Sources• Voltage Source V<name> n+ n- DC dcvalue AC acvalue• Current Source I<name> n+ n- DC dcvalue AC acvalueExamples10VDD 1 0 DC 3.3 AC 0Vdd= 3.3VGround is alwaysnode 01I1I1 1 0 DC 1n AC 0.5e-90 0.005 0.01 0.015 0.02 0.025 0.030.40.60.811.21.41.6x 10-9Time (s)Current (A)DC Value = 1nA AC Value = 0.5nA n = 1e-9 (equivalent forms)Direction of current flow10Independent Voltage and Current SourcesIndependent sources can also output functions• PULSE – Pulse function• PWL – Piecewise linear function• SIN – Sinusoidal waveform• EXP – Exponential waveform• SFFM – Single-frequency FMFor more information, see the SPICE manual (WinSPICE manual)Example – Sinusoidal voltage with a DC offset of 1V, an amplitude of 0.5V, and a frequency of 1kHz (between nodes 1 and 0)V<name> n+ n- SIN(dcvalue amplitude frequency)V1 1 0 SIN(1 0.5 1k)11• Voltage-controlled voltage source (VCVS)E<label> n+ n- nref+ nref- gain• Current-controlled current source (CCCS)F<label> n+ n- voltagesourceref gain• Voltage-controlled current source (VCCS)G<label> n+ n- nref+ nref- transconductance• Current-controlled voltage source (CCVS)H<label> n+ n- voltagesourceref transconductance• Voltage-controlled sources reference the voltage across two nodes• Current-controlled sources reference the current flowing through a voltage source– Can be a “dummy” voltage source– A voltage source with no voltage supplied– VDUMMY 3 4 DC 0 AC 0• Current sources flow from n+ to n-Dependent Voltage and Current Sources12Transistors• nFETsM<name> drain gate source bulk modelname W=value L=value• pFETsM<name> drain gate source well modelname W=value L=valueExamples (Assume models “NFET” and “PFET” are defined elsewhere)210M1 2 1 0 0 NFET W=100u L=4.8uAssume the bulk connection is tied to ground2103M2 0 1 2 3 PFET W=100u L=4.8u13Model FilesTwo major models for simulating transistors•BSIM– Great for above threshold simulations– Essentially empirical fits– Many, many parameters (upwards of hundreds)– Does not do subthreshold very well, at all• EKV Model– Mathematical model of the MOSFET operation– Much fewer parameters– Does subthreshold operation very well14EKV Model• Enz, Krummenacher, and Vittoz Model – (3 Swiss engineers who wanted a better MOSFET model, specifically for low-current applications)• Model is a “single expression” that preserves continuity of the operation• Based on the physics of the MOS device (not just empirical fits)• We will be using the 0.5µm model available at the EKV website– http://legwww.epfl.ch/ekv/ekv26_0u5.par• More information can be found at – http://legwww.epfl.ch/ekv/– Liu, et al. pg 86-8915AnalysisSeveral types of analyses can be performed• Operating point• DC sweep• AC sweep• Transient analysis• Additional useful analyses – distortion, noise, pole-zero, sensitivity, temperature, transfer functionWe will be making use of these analyses extensively16AnalysisAnalysis declaration is given by a line of code near the end of the SPICE deck• Operating point analysis (.OP)– Provides DC operating point (capacitors shorted, inductors opened)– .OP• DC sweep (.DC)– Can sweep a DC voltage or current to determine a DC transfer function– .DC sourcename startval stopval incrementval–e.g. Æ .DC VIN 0 5 0.1 (This would sweep source VIN from 0V to 5V with steps of 0.1V)17Analysis• AC analysis (.AC)– Can sweep an AC voltage or current over a specified frequency range to determine the transfer function / frequency response– Does nottake distortion and nonlinearities into account– .AC {DEC,OCT,LIN} numpoints freqstart freqstop•DEC– numpoints per decade•OCT– numpoints per octave•LIN– linear spacing of points, numpoints = total number of points–e.g. Æ .AC DEC 10 10 1E5• AC sweep from 10Hz to 100kHz, points spaced logarithmically, 10 simulation points per decade– Must have a source with an AC component in the circuit18Analysis• Transient analysis (.TRAN)– Determines the response of a circuit to a transient signal / source (sine wave, PWL function, etc.)– Allows you to achieve the most results with a simulation (distortion, nonlinearity, operation, etc.)– .TRAN timestep timestop {timestart {maxstepsize}} {UIC}– Optional