Digital Design Sequential Logic Principles Credits Slides adapted from J F Wakerly Digital Design 4 e Prentice Hall 2006 C H Roth Fundamentals of Logic Design 5 e Thomson 2004 A B Marcovitz Intro to Logic and Computer Design McGraw Hill 2008 R H Katz G Borriello Contemporary Logic Design 2 e Prentice Hall 2005 1 Sequential Circuits A sequential circuit is one whose outputs depend not only on its current inputs but also on the past sequence of inputs In other words sequential circuits must be able to remember i e store the past history of the inputs in order to produce the present output The information about the previous inputs history is called the state of the system A circuit that uses n binary state variables to store its past history can take up to 2n different states Since n is always finite sequential circuits are also called finite state machines FSM 2 How can we remember The key to build storage circuits is feedback 1 0 0 1 Cg 0 1 A storage element from Physics t t t 2 time Unfortunately caps are not ideal they lose charge dv v i t C g C g lim t 0 dt t v t v t C g lim 0 A storage element model from Calculus 3 In short sequential circuits are circuits consisting of ordinary gates and feedback loops X1 X2 Xn switching network Z1 Z2 Zn 4 The simplest sequential circuit Two inverters and a feedback loop form a static storage cell The cell will hold value as long as it has power applied 1 bistable cell state stored value 0 How to get a new value into the storage cell selectively break feedback path load new value into cell D latch remember data load stored value 5 Analog analysis of the bistable cell Vin1 Vout1 Vin2 Vout2 Vin1 Vout2 6 Latches and Flip Flops The two most popular varieties of storage cells used to build sequential circuits are latches and flip flops Latch level sensitive storage element Flip Flop edge triggered storage element Common examples of latches S R latch S R latch D latch gated D latch Common examples of flip flops D FF D FF with enable Scan FF JK FF T FF 7 S R Set Reset Latch XY 00 01 10 11 NOR 1 0 0 0 S R latch similar to inverter pair with capability to force output to 0 reset 1 or 1 set 1 R S Q QN 8 S R latch operation S 0 R 0 S 0 R 1 Q Q 0 S 1 R 0 QN 1 0 0 S 0 R 0 QN 0 1 QN 0 Q 1 1 QN 1 9 Q S R latch operation cont d hold reset set forbidden Race Both Q and QN are 0 at the same time 10 Improper S R latch operation QN Reset Hold Theoretically the circuit starts to oscillate Set Reset Set Race R S Q QN 11 R S latch analysis Break feedback path R Q QN S Q t Q t S t R t S t S t 0 0 0 0 1 1 1 1 R t 0 0 1 1 0 0 1 1 Q t 0 1 0 1 0 1 0 1 Q t 0 hold 1 0 reset 0 1 set 1 X not allowed X a k a characteristic equation Q t 0 0 X 1 1 0 X 1 R t next state equation Q t S t R t Q t Q Q S R Q 12 Theoretical R S latch behavior R Q S QN SR 10 SR 00 SR 01 SR 01 Q QN 0 1 SR 01 Q QN 1 0 SR 00 SR 10 SR 10 SR 11 State diagram states possible values transitions changes based on inputs SR 11 SR 01 possible oscillation between states 00 and 11 Q QN 0 0 SR 00 SR 11 SR 00 SR 11 SR 10 Q QN 1 1 13 Observed R S latch behavior Very difficult to observe R S latch in the 1 1 state one of R or S usually changes first Ambiguously returns to state 0 1 or 1 0 a so called race condition or non deterministic transition SR 00 SR 01 Q S QN SR 10 SR 01 Q QN 0 1 R SR 01 Q QN 1 0 SR 00 SR 10 SR 10 SR 11 SR 11 SR 00 Q QN 0 0 SR 11 SR 00 14 S R Latch timing Recovery time trec minimum delay between negating S and R for them to do not be considered simultaneous trec and tpw are related Both are a measure of how longs does it take for the latch feedback loop to stabilize Violations of tpw and trec causes metastability 15 S R Latch SN t 1 1 1 1 0 0 0 0 RN t Q t Q t Q t 1 0 0 hold 1 1 1 RN 0 0 0 reset SN 0 1 0 1 0 1 set 1 1 1 0 0 X not allowed 0 1 X SN t Q t X 1 0 0 X 1 1 0 RN t next state equation Q t S t R t Q t Q Q S R Q 16 D Latch Transparent Latch 17 D Latch Timing Parameters The D Latch eliminates the S R 1 problem of the SR latch However violations of setup and hold time still cause metastability 18 Clock signals Clocks are regular periodic signals used to specify state changes 19 D Flip Flop positive edge triggered Functional Table Truth Table More compact Truth Table D 0 1 Q 0 1 Notice the little triangle Next state equation CLK D Q inputs sampled on rising edge outputs change after rising edge 20 Timing Behavior of a DFF positive edge triggered 21 Setup and hold times for an edge triggered DFF 22 Minimum clock period T tpINV 2 ns tpFF 5 ns tsuFF 3 ns T 9 ns Example with T 9 ns T 15 ns Example with T 15 ns 23 Minimum clock period T cont d Observation thFF doesn t affect this calculation tpINV 2 ns tpFF 5 ns tsuFF 3 ns Tmin 10 ns 24 D Flip Flop negative edge triggered inputs sampled on falling edge outputs change after falling edge 25 DFF with asynchronous preset and clear 26 DFF with asynchronous preset and clear cont d 27 DFF with enable D D EN CLK 0 1 D Q CK Q Reliable alternative Do not even think about it 28 DFF with enable cont d 29 Scan DFF 30 Design for testability scan chains 31 JK Flip Flop rising edge triggered Functional Table Truth Table More Compact Truth Table JK 00 01 10 11 Q Q 0 1 Q Next state equation 32 Toggle Flip Flop rising edge triggered Truth Table T CLK T Q CK Q More compact Truth Table T 0 1 Q Q Q LK T Q 33 Activity Design a JK FF and a T FF using …