1Chapter 4The Von NeumannModelBased on slides © McGraw-HillAdditional material © 2004/2005 Lewis/Martin 4-2CSE 240Warning!This is a bottom-up course• No secrets, no magice.g., gates build on transistors, logic circuits from gates, etc.But… This is a top-down lecture• You’ll have to trust me for a couple slides• Start with very abstract discussion of computer architecture• Meet with Chapter 3 material soon4-3CSE 240What Do We Know?A LOT!!• Data representation (binary, 2’s complement, floating point, …)• Transistors (p-type, n-type, CMOS)• Gates (complementary logic)• Combinational logic circuits (PLAs), memory (latches, flip-flops, …)• Sequential logic circuits (state machines)• Simple “processors” (programmable traffic sign)What’s next?• Apply all this to traditional computing• Software interface: instructions• Hardware implementation: data path4-4CSE 240A Little Context1943: ENIAC• First general electronic computer (Presper Eckert and John Mauchly)(Or was it Atananasoff in 1939? Or Konrad Zuse in 1941?)• 18,000 tubes (had to replace 50 a day!)• Memory: 20 10-digit numbers (decimal)• Hard-wired program (via dials, switches,and cables)• Completed in 19461944: Beginnings of EDVAC• Among other improvements, includes program stored in memory• Gave birth to UNIVAC-I (1951)• Completed in 1952See Eniac by Scott McCartney24-5CSE 240Aside: Early MemoriesMercury delaylines!Q’ Q1 0M E R C U R YOutputInputSpeaker“Microphone”4-6CSE 240Context Continued: Stored Program Computer1945: John von Neumann• First Draft of a Report on EDVACSee John von Neumann and the Origins of Modern Computing by William AsprayVon Neumann Machine (or Model)• Memory, containing instructions and data• Control unit, for interpreting instructions• Processing unit, for performing arithmetic and logical operations• Input/Output units, for interacting with real world4-7CSE 240Von Neumann ModelMEMORY MAR MDR INPUT KeyboardMouseScannerDisk OUTPUT MonitorPrinterLEDDisk PROCESSING UNIT ALU TEMP CONTROL UNIT PC IR4-8CSE 240Memoryk x m array of stored bits (k is usually 2n)Address• Unique (n-bit) identifier of locationContents• m-bit value stored in locationBasic Operations• Load: read a value from a memory location• Store: write a value to a memory location•••0000000100100011010001010110110111101111001011011010001034-9CSE 240Interface to MemoryHow does processing unit get data to/from memory?MAR: Memory Address RegisterMDR: Memory Data RegisterTo read a location A1. Write the address A into the MAR2. Send a “read” signal to the memory3. Read the data from MDRTo write a value X to a location A1. Write the data X to the MDR2. Write the address A into the MAR3. Send a “write” signal to the memoryMEMORY MAR MDR 4-10CSE 240Processing UnitFunctional Units• ALU = Arithmetic and Logic Unit• Could have many functional units(some special-purpose,e.g., multiply, square root, …)• LC-3: ADD, AND, NOTRegisters• Small, temporary storage• Operands and results of functional units• LC-3: eight register (R0, …, R7)Word Size• Number of bits normally processed by ALU in one instruction• Also width of registers• LC-3: 16 bits PROCESSING UNIT ALU TEMP 4-11CSE 240Input and OutputDevices get data into and out of computerEach device has own interface• Often a set of registers like thememory’s MAR and MDR• LC-3 supports keyboard (input) and display (output)• Keyboard: data register (KBDR) and status register (KBSR)• Text display: data register (DDR) and status register (DSR)• Graphical display: later…Some devices provide both input and output• Disk, networkSoftware that controls device access• Driver INPUT KeyboardMouseScannerDisk OUTPUT MonitorPrinterLEDDisk4-12CSE 240Control UnitOrchestrates execution of the programInstruction Register (IR)• Contains the current instructionProgram Counter (PC)• Contains the address of the next instruction to executeControl Unit• Reads an instruction from memory (at PC)• Interprets the instruction• Generates signals that tell the other components what to do• Instruction may take many machine cycles to complete CONTROL UNIT PC IR44-13CSE 240LC-34-14CSE 240One More GateTri-state buffer• NOT an inverter!Allows wires to be “shared”• Alternative to mux• Only one source may drive at a time!D QEZ10Z00111001QDEZ = “high impedance” state (no current, i.e., no “pressure”) 4-15CSE 240InstructionsFundamental unit of workConstituents• Opcode: operation to be performed• Operands: data/locations to be used for operationEncoded as a sequence of bits (just like data!)• Sometimes have a fixed length (e.g., 16 or 32 bits)• Control unit interprets instructionGenerates control signals to carry out operation• Atomic: operation is either executed completely, or not at allInstruction Set Architecture (ISA)• Computer’s instructions, their formats, their behaviors4-16CSE 240Example: LC-3 ADD InstructionLC-3 has 16-bit instructions• Each instruction has a four-bit opcode, bits [15:12]LC-3 has eight registers (R0-R7) for temporary storage• Sources and destination of ADD are registers“Add the contents of R2 to the contents of R6,and store the result in R6.”54-17CSE 240Example: LC-3 LDR InstructionReads data from memoryBase + offset addressing mode• Add offset to base register to produce memory address• Load from memory address into destination register“Add the value 6 to the contents of R3 to form amemory address. Load the contents of memoryat that address and place the resulting data in R2.”4-18CSE 240Instruction ProcessingQuestion• How are instructionsexecuted?DECODE instructionEVALUATE ADDRESSFETCH OPERANDSEXECUTE operationSTORE resultFETCH instruction from mem.4-19CSE 240Instruction Processing: FETCHIdea• Put next instruction in IR & increment PCSteps• Load contents of PC into MAR• Increment PC• Send “read” signal to memory• Read contents of MDR, store in IRWho makes all this happen?• Control unitEAOPEXSFD4-20CSE 240FETCH in LC-3Load PC into MDR (inc PC)ControlData64-21CSE 240FETCH in LC-3Load PC into MDRRead MemoryControlData4-22CSE 240FETCH in LC-3Load PC into MDRRead MemoryCopy MDR into IRControlData4-23CSE 240Instruction Processing: DECODEIdentify opcode• In LC-3, always first four bits