Chip design has become too risky a businessTypical SOC ArchitectureIP re-use sounds great until you start to use it...New semantics for expressing behavior to reduce design complexityBluespec promotes compositionthrough guarded interfacesIn Bluespec SystemVerilog (BSV) …Bluespec: State and Rules organized into modulesProgramming withrules: A simple exampleGCD in BSVGCD Hardware ModuleGenerated Verilog RTL: GCDGenerated HardwareGenerated Hardware ModuleDesign a 802.11a TransmitterTransmitter OverviewReceiver OverviewIFFT RequirementsArea-Frequency TradeoffCombinational IFFTRadix-4 NodeBluespec code: Radix-4 NodeBluespec code for pure Combinational CircuitBluespec code for pure Combinational Circuit continuedPipelined IFFTBluespec code for Pipeline StageBluespec code for Pipeline StageCircular pipeline: Reusing the Pipeline StageBluespec Code for Circular PipelineBluespec Code for Circular PipelineJust one Radix-4 node!Bluespec Code for Extreme reuseBluespec Code for Extreme reuse-2Synthesis results Nirav Dave & Mike PellauerSynthesis results Steve Gerding, Elizabeth Basha & Rose LiuTwo circular pipelinesMarch 1, 2006 L-1Architecture exploration in BluespecArvind Computer Science & Artificial Intelligence LabMassachusetts Institute of TechnologyGuest Lecture 6.973 (lecture 7)Cite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].March 1, 2006 L-2Chip design has become too risky a businessEver increasing size and complexity Microprocessors: 100M gates ⇒ 1000M gates ASICs: 5M to 10M gates ⇒ 50M to 100M gatesEver increasing costs and design team sizes > $10M for a 10M gate ASIC > $1M per re-spin in case of an error (does not include the redesign costs, which can be substantial)18 months to design but only an eight-month selling opportunity in the market Fewer new chip-starts every year Looking for alternatives, e.g., FPGA’s⇒Cite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].March 1, 2006 L-3Typical SOC ArchitectureFor example: Cell phoneHardware/software development needs to be tightly coupled in order to meet performance/power/ cost goalsSystem validation for functionality and performance is very difficultStable platform for software developmentIP block reuse is essential to mitigate development costsIP = Intellectual PropertyCite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].March 1, 2006 L-4IP re-use sounds great until you start to use it...data_inpush_req_npop_req_nclkrstndata_outfullemptyExample: Commercially available FIFO IP blockNo machine verification of such informal constraints is feasibleThese constraints are spread over many pages of the documentation...Cite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].March 1, 2006 L-5New semantics for expressing behavior to reduce design complexity Decentralize complexity: Rule-based specifications (Guarded Atomic Actions) Let us think about one rule at a timeFormalize composition: Modules with guarded interfaces Automatically manage and ensure the correctness of connectivity, i.e., correct-by-construction methodology Retain resilience to changes in design or layout, e.g. compute latency ∆’s Promote regularity of layout at macro levelBluespecCite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].March 1, 2006 L-6Bluespec promotes compositionthrough guarded interfacestheModuleAnot fullnot emptynot emptynnrdyenabrdyenabrdyenqdeqfirstFIFOtheModuleBtheFifo.enq(value1);theFifo.deq();value2 = theFifo.first();theFifo.enq(value3);theFifo.deq();value4 = theFifo.first();theFifoEnqueuearbitration controlDequeuearbitration controlSelf-documenting interfaces; Automatic generation of logic to eliminate conflicts in use.Cite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].MarIn Bluespec SystemVerilog (BSV) …ch 1, 2006 L-7Power to express complex static structures and constraints Checked by the compiler“Micro-protocols” are managed by the compiler The compiler generates the necessary hardware (muxing and control) Micro-protocols need less or no verificationEasier to make changes while preserving correctnessÎ Smaller, simpler, clearer, more correct codeCite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].interfacemoduleMarcBluespec: State and Rules organized into modulesAll state (e.g., Registers, FIFOs, RAMs, ...) is explicit.Behavior is expressed in terms of atomic actions on the state:Rule: condition Î actionRules can manipulate state in other modules only via their interfaces.Cite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology.h 1, 2006 Downloaded on [DD Month YYYY].L-8March 1, 2006 L-9Programming withrules: A simple exampleEuclid’s algorithm for computing the Greatest Common Divisor (GCD):15 696subtract36subtract63swap33subtract03subtractanswer:Cite as: Vladimir Stojanovic, course materials for 6.973 Communication System Design, Spring 2006.MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts Institute of Technology. Downloaded on [DD Month YYYY].March 1, 2006 L-10GCD in BSVmodule mkGCD (I_GCD);Reg#(int) x <- mkRegU;Reg#(int) y <- mkReg(0);rule swap ((x > y) && (y != 0));x <= y; y <= x;endrulerule subtract ((x <= y) && (y != 0));y <= y – x;endrulemethod Action start(int a, int b) if(y==0);x <= a; y <= b;endmethodmethod int result() if (y==0);return