CMSC 611: AdvancedCMSC 611: AdvancedComputer ArchitectureComputer ArchitectureDesign LanguagesDesign LanguagesPractically everything adapted from slides by Peter J. Ashenden, VHDL Quick Start Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slidesAbstraction Hierarchy ofAbstraction Hierarchy ofDigital DesignDigital Design• Digital designers often employ abstraction hierarchy, which canbe expressed in two domains:– Structural domain: Components are described in terms of aninterconnection of more primitive components– Behavior domain: Components are described by defining the theirinput/output responses by means of a procedureStrcuturalDecompositionBehavioralDecompositionSiliconCircuitGat eRegisterChipPMSIncreased compexity and detailsLevelStructuralPrimitiveBehaviorRepresentationPMSCPU, memories,busesPerformancespecificationsChipMicroprocessor,RAM, UARTI/O response,algorithmsRegisterALU, counter,MUXTruth table, statetableGateAND, OR, flip-flopBooleanequationsCircuitTransistor, R, L,and CDifferentialequationsSiliconGeometricalobjectsProcessspecifications.Design's Levels of AbstractionDesign's Levels of AbstractionSimulation continues untilthe event queue is emptyor stopped externally bythe designerDesign SimulatorDesign Simulator• Device behavioral model is represented by procedure calls• Events within the simulator are kept in a time-based queue• Events stored as three-tuples (Module #, Pin #, New logic value)• Depending on the behavioral model of a module, the handling of anevent usually trigger other events that will be inserted in the event queueModule 2Module 3Module 1Module 0100 ns6380, 6, 1- - - - -- - - - -- - - - -- - - - -- - - - -1, 8, 0EventQu eueEventsTime0- -- -- -- -- -100high level ofabstractionFunctionalStructuralGeometric“Y-chart” due to Gajski & Kahnlow level ofabstractionDomains and Levels ofDomains and Levels ofModelingModelingDomains and Levels ofDomains and Levels ofModelingModelingFunctionalStructuralGeometricAlgorithm(behavioral)Register-TransferLanguageBoolean EquationDifferential Equation“Y-chart” due to Gajski & KahnDomains and Levels ofDomains and Levels ofModelingModelingFunctionalStructuralGeometricProcessor-MemorySwitchRegister-TransferGateTransistor“Y-chart” due to Gajski & KahnDomains and Levels ofDomains and Levels ofModelingModelingFunctionalStructuralGeometricPolygonsSticksStandard CellsFloor Plan“Y-chart” due to Gajski & KahnHardware Design LanguagesHardware Design Languages• A hardware design language providesprimitives for describing both structural andbehavioral models of the design• Hardware design languages are useful in– Documenting and modeling the design– Ensuring design portability• Every hardware design language is supportedby a simulator that helps in:– Validating the design– Mitigating the risk of design faults– Avoiding expensive prototyping for complicatedhardwareVHDL &VHDL & Verilog Verilog• VHDL and Verilog are the most famousand widely used hardware designlanguage• Focus on VHDL:– Interfaces, Behavior, Structure, TestBenches– Analysis, Elaboration, Simulation, SynthesisModeling Digital SystemsModeling Digital Systems• VHDL is for writing models of a system• Reasons for modeling– requirements specification– documentation– testing using simulation– formal verification– synthesis• Goal– most reliable design process, with minimum cost and time– avoid design errors!Modeling InterfacesModeling Interfaces• Entity declaration– describes the input/output ports of a moduleentity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;q0, q1, q2, q3 : out bit );end entity reg4;entity name port names port mode (direction)port typereserved wordspunctuationVHDL-87VHDL-87• Omit entity at end of entity declarationentity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;q0, q1, q2, q3 : out bit );end reg4;Modeling BehaviorModeling Behavior• Architecture body– describes an implementation of an entity– may be several per entity• Behavioral architecture– describes the algorithm performed by themodule– contains• process statements, each containing• sequential statements, including• signal assignment statements and• wait statementsBehavior ExampleBehavior Examplearchitecture behav of reg4 isbeginstorage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;beginif en = '1' and clk = '1' thenstored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;end if;q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;wait on d0, d1, d2, d3, en, clk;end process storage;end architecture behav;Modeling StructureModeling Structure• Structural architecture– implements the module as a composition ofsubsystems– contains• signal declarations, for internal interconnections– the entity ports are also treated as signals• component instances– instances of previously declared entity/architecture pairs• port maps in component instances– connect signals to component ports• wait statementsStructure ExampleStructure Exampleint_clkd0d1d2d3enclkq0q1q2q3bit0d_latchdclkqbit1d_latchdclkqbit2d_latchdclkqbit3d_latchdclkqgateand2abyStructure ExampleStructure Example• First declare D-latch and and-gate entities andarchitecturesentity d_latch isport ( d, clk : in bit; q : out bit );end entity d_latch;architecture basic of d_latch isbeginlatch_behavior : process isbeginif clk = ‘1’ thenq <= d after 2 ns;end if;wait on clk, d;end process latch_behavior;end architecture basic;entity and2 isport ( a, b : in bit; y : out bit );end entity and2;architecture basic of and2 isbeginand2_behavior : process isbeginy <= a and b after 2 ns;wait on a, b;end process and2_behavior;end architecture basic;Structure ExampleStructure Example• Now use them to implement a registerarchitecture struct of reg4 issignal int_clk : bit;beginbit0 : entity work.d_latch(basic)port map ( d0, int_clk, q0 );bit1 : entity work.d_latch(basic)port map ( d1, int_clk, q1 );bit2 : entity work.d_latch(basic)port map ( d2, int_clk, q2 );bit3 : entity work.d_latch(basic)port map ( d3, int_clk, q3 );gate : entity work.and2(basic)port map ( en, clk, int_clk );end architecture struct;Mixed Behavior and StructureMixed Behavior and Structure• An architecture can contain bothbehavioral and structural parts– process statements and componentinstances• collectively called concurrent statements–