U of I CS 232 - Stalls and flushes (30 pages)

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Stalls and flushes



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Stalls and flushes

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Lecture Notes


Pages:
30
School:
University of Illinois
Course:
Cs 232 - Computer Architecture II
Computer Architecture II Documents

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Stalls and flushes Last time we discussed data hazards that can occur in pipelined CPUs if some instructions depend upon others that are still executing Many hazards can be resolved by forwarding data from the pipeline registers instead of waiting for the writeback stage The pipeline continues running at full speed with one instruction beginning on every clock cycle Today we ll see some real limitations of pipelining Forwarding may not work for data hazards from load instructions Branches affect the instruction fetch for the next clock cycle In both of these cases we may need to slow down or stall the pipeline October 17 2007 2003 Craig Zilles derived from slides by Howard Huang 1 Data hazard review A data hazard arises if one instruction needs data that isn t ready yet Below the AND and OR both need to read register 2 But 2 isn t updated by SUB until the fifth clock cycle Dependency arrows that point backwards indicate hazards sub 2 1 3 and 12 2 5 or 13 6 2 October 17 2007 1 2 IM Reg IM Clock cycle 3 4 DM Reg IM Stalls and flushes 5 7 Reg DM Reg 6 Reg DM Reg 2 Forwarding to the rescue The desired value 1 3 has actually already been computed it just hasn t been written to the registers yet Forwarding allows other instructions to read ALU results directly from the pipeline registers without going through the register file sub 2 1 3 and 12 2 5 or 13 6 2 October 17 2007 1 2 IM Reg IM Clock cycle 3 4 DM Reg IM Stalls and flushes 5 7 Reg DM Reg 6 Reg DM Reg 3 What about loads Imagine if the first instruction in the example was LW instead of SUB How does this change the data hazard lw 2 20 3 and 12 2 5 October 17 2007 1 2 Clock cycle 3 4 IM Reg DM IM Reg Stalls and flushes 5 Reg DM 6 Reg 4 What about loads Imagine if the first instruction in the example was LW instead of SUB The load data doesn t come from memory until the end of cycle 4 But the AND needs that value at the beginning of the same cycle This is a true data hazard the data is not available when we need it lw



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