COMPARISON OF PERFORMANCE PARAMETERS OF SRAM DESIGNS IN 160m CMOS AND CNTFET TECHNOLOGIES Anuj Pushkama, Sajna Raghavan and Hamid Mahmoodi School of Engineering, San Francisco State University San Francisco, CA, USA Email: {anujp, sajju, mahmoodi}@sfsu.edu Abstract: CMOS devices are scaling down to nano ranges resulting in increased process variations and short channel effects which not only affect the reliability of the device but also performance expectations. Carbon Nanotube Field Effect Transistor (CNTFET) is a very promising and superior technology for its applications to circuit design. In this paper we intend to evaluate and compare the performance parameters of a traditional 6T SRAM cell between a predictive 16nm Complementary Metal Oxide Semiconductor (CMOS) technology and CNTFET. The model used to simulate CNT transistor is a tentative model from the researchers of Stanford University, which is not yet practically implemented. Since the dimensions of MOSFETS are reduced aggressively, it is essential to know the potential of what both the technologies have to offer, with their least dimensions available. The SRAM design uses the smallest transistors possible and is also susceptible to reliability issues and process variations, making it an ideal benchmark circuit to compare the two technologies. Our simulations results show that CNTFET based SRAM design is a viable design to choose compared to its CMOS counterpart. The results show that there is a 52.7% increase in SNM of the memory cell. Meanwhile, the cell becomes 5% faster. These results clearly justify that CNTFET is more suitable for circuit design rather than MOSFETs, although both the models under consideration are predictive models. This comparative study would definitely help us choose better technology alternatives in near future. I. INTRODUCTION Over recent years the scaling in CMOS technology has been very aggressive. With ultra-thin dimensions, the technology is facing many critical challenges and reliability issues. Aggressive scaling has resulted in augmented short channel effects, exponential rise in leakage currents, process variations, depressed gate control for transistors and hysterical power densities. Ultrathin CMOS technologies have been predicted and modeled for decades. Recently predicted models of order of 22nm and 16nm in Bulk CMOS have been suggested [6]. Moreover, Carbon nanotubes (CNT) have been identified with highest potential risk-benefit ratio for emerging logic applications such as nano field-effect transistors (nano-FETs). Meanwhile several major technology related questions still need to be addressed. In particular the possibility to obtain ballistic transport over several hundred nanometers at room temperature together with a very large Fermi velocity of around 10 cm/s allows for high-performance on-state characteristics. The CNTFETs also have a significantly smaller off current, which greatly reduces the power consumption in standby states. Recently, S. Lin, in [2] proposed a SRAM cell de-sign comparison using 32nm CMOS and predicted CNTFET (20nm) based technologies. Characteristics of SRAM were investigated and quantified. These studies predict superior performance of CNTFET based SRAM when compared to conventional Si based MOSFET on the basis of Access time, Static Noise margin (SNM) [3] and Leakage power. The study lacked the comparison of models based on Temperature, which is one of the very critical and dominant environmental factors on performance. Very recently 978-1-4244-6683-2/101$26.00 ©2010 IEEE 339 predicted model of 16nm High K metal gate [6] has substantially increased the choice of device models for circuit designing. It is essential to know the potential of what both the technologies have to offer, with their least dimensions available, i.e. for CMOS of 16nm and CNTFET model of 10nm. In our research we use the predicted model for CNTFET, proposed by re-searchers from Stanford University [1], which gave us the opportunity to use minimum channel length of CNTFET as IOnm. The Static Random Access Memory (SRAM) is an ideal benchmark circuit to compare the two technologies. We use a traditional 6T SRAM cell structure to compare the two highlighted technologies, because the SRAM design is sensitive to transistor density (using smallest transistors possible) and reliability issues. We have used Hspice simulation to analyze and report the results of SRAM cell using each model. The paper is organized as follows. Section II gives a short description about the CNTFET based model that is developed by the researchers from Stanford University [1]. Section III talks about the current-voltage (IV) characteristics of the CNTFET under temperature variation and comparison with CMOS. This section reflects some physical insight behind the CNTFET model that we have used. Section III describes the traditional 6T SRAM structure. This also underlines some important design constraints and parameters that were essential for the re-search and the results. Section V, and VI show our simulation results and the conclusion of our research. II. CARBON NANOTUBE FIELD EFFECT TRAN-SISTORS DEVICE MODEL Figure I: 3-D Structure ofCNTFET III The Figure 1 shows a 3-D device structure of Carbon Nanotube Field Effect Transistor (CNTFET) with multiple channels, high K metal gate and parasitic gate capacitances. There are three transistors fabricated along one Carbon Nano tube. As described in the Introduction, we use a circuit-compatible compact model for the intrinsic channel region of the MOSFET like single walled carbon nanotube field effect transistor (CNTFETs). This model can be used for wide range of diameters and other structural variables. In the model itself, the global device parameters of the transistor have been kept constant and were suggested not to be altered. The model has two variants:V-I Characteristics of N type CNTFET l.OOE+OO 2.00E-oS l.OOE-ol 1.80E-oS l.00E-02 l.60E-oS