FEATURESAPPLICATIONS GENERAL DESCRIPTIONFUNCTIONAL BLOCK DIAGRAMTABLE OF CONTENTSREVISION HISTORYSPECIFICATIONSTIMING CHARACTERISTICSTiming DiagramABSOLUTE MAXIMUM RATINGSTHERMAL CHARACTERISTICSESD CAUTIONPIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSTYPICAL PERFORMANCE CHARACTERISTICSTHEORY OF OPERATIONREFERENCE INPUT SECTIONRF INPUT STAGEN COUNTERN and R RelationshipR COUNTERPHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMPMUXOUT AND LOCK DETECTLock DetectINPUT SHIFT REGISTERLATCH MAPS AND DESCRIPTIONSLATCH SUMMARY REFERENCE COUNTER LATCH MAP N COUNTER LATCH MAPFUNCTION LATCH MAPINITIALIZATION LATCH MAPFUNCTION LATCHCounter ResetPower-DownMUXOUT ControlFastlock Enable Bit Fastlock Mode BitFastlock Mode 1Fastlock Mode 2Timer Counter ControlCharge Pump CurrentsPD PolarityCP Three-StateINITIALIZATION LATCHDevice Programming After Initial Power-UpInitialization Latch MethodCE Pin MethodCounter Reset MethodAPPLICATIONSVERY LOW JITTER ENCODE CLOCK FOR HIGH SPEED CONVERTERS PFDINTERFACING ADuC812 InterfaceADSP21xx InterfacePCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGEOUTLINE DIMENSIONSORDERING GUIDEPhase Detector/Frequency Synthesizer ADF4002 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. FEATURES 400 MHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 104 MHz phase detector APPLICATIONS Clock conditioning Clock generation IF LO generation GENERAL DESCRIPTION The ADF4002 frequency synthesizer is used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, and programmable N divider. The 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). In addition, by programming R and N to 1, the part can be used as a standalone PFD and charge pump. FUNCTIONAL BLOCK DIAGRAM CLKDATALEREFINRFINARFINB24-BIT INPUTREGISTERSDOUTAVDDDVDDCEAGNDDGND14-BITR COUNTERR COUNTERLATCH2214FUNCTIONLATCHN COUNTERLATCH13-BITN COUNTERM3 M2 M1MUXSDOUTAVDDHIGH ZMUXOUTCPGNDRSETVPCPPHASEFREQUENCYDETECTORLOCKDETECTREFERENCECHARGEPUMPCURRENTSETTING 1ADF4002CPI3 CPI2 CPI1CPI6 CPI5 CPI4CURRENTSETTING 206052-001 Figure 1.ADF4002 Rev. A | Page 2 of 20 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 Reference Input Section............................................................... 8 RF Input Stage............................................................................... 8 N Counter...................................................................................... 8 R Counter ...................................................................................... 8 Phase Frequency Detector (PFD) and Charge Pump.............. 8 MUXOUT and Lock Detect.........................................................9 Input Shift Register .......................................................................9 Latch Maps and Descriptions ....................................................... 10 Latch Summary........................................................................... 10 Reference Counter Latch Map.................................................. 11 N Counter Latch Map................................................................ 12 Function Latch Map................................................................... 13 Initialization Latch Map ............................................................ 14 Function Latch............................................................................ 15 Initialization Latch ..................................................................... 16 Applications..................................................................................... 17 Very Low Jitter Encode Clock for High Speed Converters... 17 PFD............................................................................................... 17 Interfacing ................................................................................... 17 PCB Design Guidelines for Chip Scale Package .................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19 REVISION HISTORY 4/07—Rev. 0 to Rev. A Changes to Features