4-BIT ARITHMETIC LOGIC UNIT Motorola MC54/74F181AgendaAbstractIntroductionProject SummaryDesign Flow and Cost AnalysisALU Block Diagram with Long pathMC54/74F181 Function TableLongest Path CalculationsDFF SizingSchematicSchematic with DFF (Top-Level)LayoutVerification(LVS)NC Verilog simulation (Logic)NC Verilog simulation (Arithmetic)Simulations(Logic Function)Simulations(Arithmetic Function)POWERLessons LearnedSummaryAcknowledgements14-BIT ARITHMETIC LOGIC UNITMotorola MC54/74F181Heungyoun Kim Lu GaoJun Li Advisor: Dr. David W. Parent DATE: 12/05/20052Agenda•Abstract•Introduction–Why–Simple Theory–Background information•Summary of Results•Project (Experimental) Details•Lessons Learned•Summary•Acknowledgement3Abstract•The MC54/74F181 is a 4-bit high speed parallel Arithmetic Logic Unit which uses full Carry Lookahead for high speed arithmetic operation. It can perform 16 logic operations or 16 arithmetic operations.•We designed a 4-bit ALU that : Operating frequency = 200 MHz Area = 340x310m2 Power = 15.9mW4Introduction•The Arithmetic and Logic Unit ( ALU ) is a fundamental block of microprocessor.•Design consists of different kinds of logic : Carry Lookahead Adder, AOI, XOR, DFF, NAND, NOR, etc. We can practice all the circuits learned from the textbook.•Strictly follow “Design Flow” to understand the Full-Custom design.•Provide a good starting point to move on to more advanced IC design.5Project Summary•We designed a 4-bit ALU based on Motorola MC54/74F181 operating at 200 MHz. •Designed the sequential logic circuit: DFF.•Total area is 340x310um2. •Power dissipation is 15.9mW.6Design Flow and Cost AnalysisS p e c i f i c a t i o nV e r i f y l o g i c i n N C - V e r i l o gF i n d l o n g p a t h /T r a n s i s t o r s i z i n gS c h e m a t i c / S p i c eS i m u l a t i o nC e l l - b a s e d l a y o u ta n d i n t e g r a t i o nD R C , E x t r a c t , L V SP o s t e x t r a c t i o n1 W e e k1 W e e k1 W e e k2 W e e k s2 W e e k s1 W e e k7ALU Block Diagram with Long path8MC54/74F181 Function Table9 Longest Path Calculations Start with even Tphl (5ns/(13+4)) for each logic level, then reassign Tphl, e.g. steal time from inverter for XOR, to get reasonable WN and WP. Since AOI33 drives about 135 fF of Cg (fanout is 8), in order to meet timing and at the same time get the reasonable WN and WP, we add two inverters behind AOI33. Cell Bit# Cg+Cint (f F) Cint=20fF Tphl(ps) Targeted WN (um) WP (um) Tphl(ps) Schematic Tphl(ps) Extracted NOR2 1 50 333.333 2.1 4.95 329.235 284.78 AND4 NAND2_B 2 31.8251 294.118 2.1 2.4 318.702 318.702 XOR(AOI) 3 35.2026 416.667 1.95 3 XOR INV 4 35.2026 125 1.5 2.25 515 456 INV_B 5 26.4483 125 2.7 4.05 122.9 117.718 NAND2_A 6 31.221 250 2.7 3 250.511 220.749 NOR4 NOR2_B 7 29.617 250 2.1 5.25 253.998 217.43 NOR2_A 8 32.3515 294.118 1.8 4.2 304.47 262.06 AND5 NAND3 9 30.0872 294.118 4.65 4.05 270.12 211.89 INV 10 135.803 277.778 3.9 6.3 INV 11 37.0491 125 3.45 5.4 AOI33 AOI33 12 34.6897 714.286 3.45 4.2 1062 878 INV_A 13 45.3419 125 3.9 6.45 127 123 Total Delay ( Logic ) 3624.418 3553.936 3090.32910DFF Sizing Cell Bit# Cg+Cint (f F) Tphl(ps) Targeted WN (um) WP (um) Tphl(ps) Schematic Tphl(ps) Extracted NAND_ slave 1 37.563 5.7 4.65 Driver_ mux_slave 2 27.894 713 3.75 6 637 625 NAND_ master 3 26.197 4.2 4.5 DFF Driver_ mux master 4 15.919 655 5.55 11.5 598 592 Total delay ( DFF ) 1368 1235 1217 Tphl(ns) Targeted Tphl(ns) Schematic Tphl(ns) Extracted Total delay of logic 3.624 3.554 3.090 Total delay of DFF 1.368 1.235 1.217 Total delay 4.992 4.789 4.30711Schematic12Schematic with DFF (Top-Level)13LayoutVddGndRSETCLKDFFDFFLogic14Verification(LVS)15NC Verilog simulation (Logic)S=0110, A=0000, B=0101 F= AB = 010116 NC Verilog simulation (Arithmetic)S=0110, A=0000, B=0101 F= A minus B minus 1 = 101017Simulations(Logic Function)A3A2A1A0 = 1010B3B2B1B0 = 1001M=1Cin=1---------------------------S3S2S1S0 = 1111F= A = 1010S3S2S1S0 =1010F= B = 1001 S3S2S1S0 =0101F= B’ = 0110S3S2S1S0 =0000F= A’ = 010118Simulations(Arithmetic Function)A3A2A1A0 = 1010B3B2B1B0 = 1001M=0Cin=1-----------------------------S3S2S1S0 = 1111F= A minus 1= 1001S3S2S1S0 =1010F= (A+B’) plus AB = 0110 S3S2S1S0 =0101F= (A+B) plus AB’ = 1101S3S2S1S0 =0000F= A = 101019POWERPower = 47.77 mW / 3 clocks = 15.9 mW20Lessons Learned•Organize data and keep track of schedule.•Use cell based design and uniform cell height. •Draw a floor plan including route of power and major signals before you layout.•Do DRC often and LVS for each cell.21Summary•Our design met all the specifications, speed 200 MHz, area 340 x 310 µm2, and power dissipation 15.9mW. •Learned how to design, simulate and implement static CMOS circuits with delay constraint in transistor level using the AMI06 process. •Theory and CDS tool experience learned through this project would be a great stepping stone to the upper level design project and career.22Acknowledgements•Thanks to our families for all their support.•Thanks to Prof. David W. Parent for his help.•Thanks to Cadence Design Systems for the VLSI lab.•Thanks to Hummingbird for the great remote
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