SJSU EE 270 - Syllabus (5 pages)

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Syllabus



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Syllabus

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Lecture Notes


Pages:
5
School:
San Jose State University
Course:
Ee 270 - Advanced Logic Design
Advanced Logic Design Documents

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EE 270 Spring 2009 San Jose State University Department of Electrical Engineering Course Title Advanced Logic Design Meeting MW Lab 18 00 19 15 Engr 405 Open Lab E389 E291 Instructor Dr Tri Caohuu ENG 375 Email caohuut email sjsu edu Tel 408 924 3951 Course Outline This course presents principles and techniques in logic design design and analysis of combinational logic circuit flip flop properties sequential circuit analysis and synthesis algorithmic state machines asynchronous circuit design and analysis and design for testability The students are required to do exercises and a design project in the open laboratory using HDL based methodology The course is intended for senior students and beginning graduate student in the digital design concentration Text 1 Digital Logic Circuit Analysis and Design V P Nelson H T Nagle B D Carroll J D Irwin H Prentice Hall 1995 4 Asynchronous Circuit Design Chris J Myers Prentice Hall 2001 Ref Text 1 Digital Principles and Design Donald Givone McGrawHill 2003 2 Contemporary Logic Design Randy h Katz and Gaetano Borriello Prentice Hall 2005 Grading policy Midterm Projects Final Exam 30 30 40 Office Hours MW 15 00 17 30 Open Laboratory E 289 E291 Unix based and E 389 PC based Page 1 EE 270 Spring 2009 COURSE OUTLINE I II III IV V Introduction Week 1 and 2 Review of switching algebra Analysis and synthesis of combinational logic Synchronous vs asynchronous circuits HDL tools Simplification of switching functions Week 3 and 4 Karnaugh Maps Quine McCluskey method Espresso Algorithm Synchronous circuit design Week 5 6 7 8 Sequential devices Analysis and synthesis of synchronous sequential circuits Simplification and Optimization of Sequential Circuit Asynchronous sequential circuits Week 10 11 12 13 Huffman Circuit Muller Circuit Timed Circuit Petri net and Graph based Methods Transformation Methods Asynchronous data path pipelines Verification Introduction to design for testability Week 14 15 Fault models Combinational circuit testing



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