NYIT EENG 494 - HDL Design Principles for VLSI/FPGAs

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EEGN-494 HDL Design Principles for VLSI/FPGAsNaming Conventions and Labeling (1)Naming and Labeling (2)Free FormatComments: A must for Code Readability; Use them wiselyRecapping: Entity DeclarationMode InMode outMode out with signalMode inout – Infers bi-directionality: Under most circumstances avoid using this constructMode buffer : This construct not synthesis friendly (dependent on specific tools)Summarizing: Port ModesSlide 13STD_LOGICSTD_LOGIC type demystifiedMore on STD_LOGIC Meanings (1)More on STD_LOGIC Meanings (2)More on STD_LOGIC Meanings (4)Resolving logic levelsSignals: ElaboratedStandard Logic VectorsVectors and ConcatenationSlide 23VHDL Design StylesSlide 25Entity xor3Dataflow DescriptionDataflow Architecture (xor3 gate)Structural Architecture (xor3 gate)Component and Instantiation (1)Component and Instantiation (2)Structural DescriptionBehavioral Architecture (xor3 gate)Behavioral DescriptionConcurrent Statements vs. Sequential StatementsSequential CodeExample of Concurrent CodeExample of Concurrent Code: Using WHEN / ELSEExample of Concurrent Code: Using WITH / SELECT / WHENBLOCKSlide 41BLOCK: SimpleBLOCK: GuardedSlide 44Slide 45Assignment 2Assignment 2 continuedKazi Fall 2006 EEGN 494 1EEGN-494HDL Design Principles for VLSI/FPGAsKhurram KaziSome of the slides were taken from K Gaj’s lecture slides from GMU’s VHDL course webpage2Kazi Fall 2006 EEGN 494Naming Conventions and Labeling (1)VHDL is not case sensitiveExample:Names or labelsdatabusDatabusDataBusDATABUSare all the same3Kazi Fall 2006 EEGN 494Naming and Labeling (2)General rules of thumb (according to VHDL-87)1. All names should start with an alphabet character (a-z or A-Z)2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)5. All names and labels in a given entity and architecture must be unique4Kazi Fall 2006 EEGN 494Free FormatVHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:if (a=b) thenorif (a=b) then orif (a =b) thenare all equivalent5Kazi Fall 2006 EEGN 494Comments: A must for Code Readability; Use them wiselyComments in VHDL are indicated with a “double dash”, i.e., “--”Comment indicator can be placed anywhere in the lineAny text that follows in the same line is treated as a commentCarriage return terminates a commentNo method for commenting a block extending over a couple of linesExamples:-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFO6Kazi Fall 2006 EEGN 494Recapping: Entity Declaration Entity Declaration describes the interface of the component, i.e. input and output ports.ENTITY nand_gate ISPORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC );END nand_gate;Reserved wordsEntity namePort namesPort typeSemicolonNo SemicolonPort modes (data flow directions)7Kazi Fall 2006 EEGN 494Mode InaEntityPort signalDriver residesoutside the entity8Kazi Fall 2006 EEGN 494Mode outEntityPort signalDriver residesinside the entityCan’t read out within an entityzc <= zc9Kazi Fall 2006 EEGN 494Mode out with signalPort signalEntityDriver residesinside the entitySignal X can beread inside the entityxczz <= xc <= x10Kazi Fall 2006 EEGN 494Mode inout – Infers bi-directionality: Under most circumstances avoid using this constructSignal can beread inside the entityEntityPort signalDriver may resideboth inside and outsideof the entityaUse this construct in modeling bi-directional pads.11Kazi Fall 2006 EEGN 494Mode buffer : This construct not synthesis friendly (dependent on specific tools)EntityPort signalDriver residesinside the entityPort signal Z can beread inside the entityczc <= z12Kazi Fall 2006 EEGN 494Summarizing: Port ModesThe Port Mode of the interface describes the direction in which data travels with respect to the componentIn: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment.Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment. Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment. Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator13Kazi Fall 2006 EEGN 494STD_LOGIC Demystified14Kazi Fall 2006 EEGN 494STD_LOGICWhat is STD_LOGIC you ask?LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY nand_gate ISPORT( a : IN STD_LOGIC;b : IN STD_LOGIC; z : OUT STD_LOGIC);END nand_gate;ARCHITECTURE model OF nand_gate ISBEGINz <= a NAND b;END model;15Kazi Fall 2006 EEGN 494STD_LOGIC type demystified Value Meaning ‘X’ Forcing (Strong driven) Unknown‘0’ Forcing (Strong driven) 0‘1’ Forcing (Strong driven) 1‘Z’ High Impedance‘W’ Weak (Weakly driven) Unknown‘L’Weak (Weakly driven) 0.Models a pull down.‘H’Weak (Weakly driven) 1. Models a pull up.‘-’ Don't Care16Kazi Fall 2006 EEGN 494More on STD_LOGIC Meanings (1)‘1’‘0’‘X’Contention on the busX17Kazi Fall 2006 EEGN 494More on STD_LOGIC Meanings (2)Output drive buffers in High Impedance state (also known to be in tri-state): Used when multiple drivers on the same wire or bus18Kazi Fall 2006 EEGN 494More on STD_LOGIC Meanings (4)•Do not care.•Can be assigned to outputs for the case of invalid inputs(may produce significant improvement in resource utilization after synthesis).•Use with caution ‘1’ = ‘-’ give FALSE‘-’19Kazi Fall 2006 EEGN 494Resolving logic levels X 0 1 Z W L H -X X X X X X X X X0 X 0 X 0 0 0 0 X1 X X 1 1 1 1 1 XZ X 0 1 Z W L H XW X 0 1 W W W W XL X 0 1 L W L W XH X 0 1 H W W H X- X X X X X X X X20Kazi Fall 2006 EEGN 494Signals: Elaborated SIGNAL a : STD_LOGIC;SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO


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NYIT EENG 494 - HDL Design Principles for VLSI/FPGAs

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