EE345L Fall 2008 Final Page 1 of 12 Jonathan W. Valvano First:_________________ Last:_____________________ This is the closed book section. You must put your answers in the boxes on this answer page. When you are done, you turn in the closed-book part and can start the open book part. Address Bit 7 6 5 4 3 2 1 Bit 0 Name $0082 ADPU AFFC ASWAI ETRIGLE ETRIGP ETRIG ASCIE ASCIF ATDCTL2 $0083 0 S8C S4C S2C S1C FIFO FRZ1 FRZ0 ATDCTL3 $0084 SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 ATDCTL4 $0085 DJM DSGN SCAN MULT 0 CC CB CA ATDCTL5 $0086 SCF 0 ETORF FIFOR 0 CC2 CC1 CC0 ATDSTAT0 $008B CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 ATDSTAT1 $0090-1 Bit 15 14 13 12 11 10 Bit 0 ATDDR0 $0092-3 Bit 15 14 13 12 11 10 Bit 0 ATDDR1 $0094-5 Bit 15 14 13 12 11 10 Bit 0 ATDDR2 $0096-7 Bit 15 14 13 12 11 10 Bit 0 ATDDR3 $0098-9 Bit 15 14 13 12 11 10 Bit 0 ATDDR4 $009A-B Bit 15 14 13 12 11 10 Bit 0 ATDDR5 $009C-D Bit 15 14 13 12 11 10 Bit 0 ATDDR6 $009E-F Bit 15 14 13 12 11 10 Bit 0 ATDDR7 (5) Question 1. Write a C function that samples ADC channel 4. Convert the 10-bit ADC sample to a fixed-point voltage with a resolution of 0.001V. For example, if the voltage on PAD4 is 1.234567V, return an integer somewhere in the range of 1230 to 1240. Assume the ADC is already initialized for a 10-bit sample, sequence length is 1, and the ADC clock is 2 MHz. Minimize errors due to dropout and overflow. Use busy-wait synchronization.EE345L Fall 2008 Final Page 2 of 12 (5) Question 2. Consider the situation in which the output of one digital circuit is connected to the inputs of two other digital circuits. There are no other connections on this signal, i.e., one output is tied to two inputs. The output specifications of the first circuit are VOH, VOL, IOH and IOL. The input specifications of the second and third circuits are VIH, VIL, IIH and IIL. These are the specifications, like you would find in a data sheet, not actual measurements of voltage and current like you would measure in lab with a DVM. First Digital CircuitSecond Digital CircuitThird Digital Circuit Give the four inequalities relating these eight parameters that must be true in order for the interface to operate properly. It may be necessary to also add numbers to these inequalities. VOH VIH |IOH| |IIH| VOL VIL |IOL| |IIL| (5) Question 3. There are three input parameters: x0, x2, and y2, containing three 8-bit ADC samples. The sampling rate is 240 Hz. x0 is the current 8-bit ADC sample, x2 is the 8-bit ADC sample collected two times ago, and y2 is the 8-bit output of the filter two times ago. Even though the parameters are defined as 16-bit signed integers, you may assume all four numbers are integers ranging from 0 to 255. There is an output parameter (y), which implements a high-Q 60 Hz digital notch filter. In other words, this equation will remove all 60 Hz components from the sampled data. All four variables are typed as short. Write C code to implement this digital filter without using floating point. Hint 0.78125 = 25/32, and 0.5625 = 18/32. Maximize for speed and minimize errors due to dropout and overflow. Just write C code to implement this equation, not the ADC sampling or the data structure that shifts the data. y = 0.78125*x0 + 0. 78125*x2 – 0.5625*y2EE345L Fall 2008 Final Page 3 of 12 (5) Question 4. The control pin is interfaced to Port T bit 2, and the clock and data are connected to the SPI. The clock and data are created by the real SPI, and the control signal is bit-banged. On the 9S12C32 clock is SCK=PM5, and the data is MOSI=PM4. On the 9S12DP512 clock is SCK=PS6, the data is MOSI=PS5. Write a C function that outputs (transmits) one byte using the SPI port. You may assume the SPI is already initialized with the 9S12 as master, and PT2 is an output. Use busy-wait synchronization. Address Bit 7 6 5 4 3 2 1 Bit 0 Name $00D8 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBF SPICR1 $00D9 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0 SPICR2 $00DA 0 0 0 0 0 SPR2 SPR1 SPR0 SPIBR $00DB SPIF 0 SPTEF MODF 0 0 0 0 SPISR $00DD Bit 7 6 5 4 3 2 1 Bit 0 SPIDR clockdatacontrolEE345L Fall 2008 Final Page 4 of 12 (5) Question 5. This problem addresses the issue of capacitive loading on a high-speed serial transmission line like SPI. The SPI ports of two 9S12s are connected with a VERY long cable. We will model this cable as a single resistor in series with a capacitor, as shown in the figure below. For this question, assume an ideal transmitter (output impedance of 0) and an ideal receiver (input impedance of infinity). Let R = 1 Ω, and C = 10 nF. Note that R*C is 10 ns. Consider a 5-V 100-ns pulse on the output of the transmitter (labeled as Vin ) (as might occur with a 5-Mbps SPI transmission) Vintime500 100ns Derive an equation for Vout as a function of time for the first 100 ns. Show your work and plug in for R*C equals 10 ns. V i nRVoutTr a n s m i t t e r ReceiverCEE345L Fall 2008 Final Page 5 of 12 (5) Question 6. Consider this situation. You are a new employee assigned to test an existing product. During the testing of the device, you think you discover a possible fault in the system that might result in the compromise of safety. To whom do you first report this fault? Why? (5) Question 7. The main program synthesizes a waveform (defines a sequence of DAC output values) and a periodic output compare interrupt will output the data to the DAC separated by a fixed time. A FIFO queue is used to buffer data between a main program (e.g., main program calls DAC_Out, which in turn calls Fifo_Put). An output compare interrupt service routine calls Fifo_Get and actually writes to the DAC. Experimental observations show this FIFO is usually empty, and has at most 3 elements. What does it mean? Choose A-F. A) The system is CPU bound B) Bandwidth could be increased by increasing FIFO size C) The system is I/O bound D) The FIFO could be replaced by a global variable E) The latency is small and bounded ___________ F) Interrupts are not needed in this system (5) Question 8. RDRF interrupts are armed so that interrupts occur when new data arrives into the 9S12. Consider the situation in which a FIFO queue is used to buffer data between the RDRF ISR and the main program. The SCIhandler